Synthesis and Netlist Viewers Resource Center
Quartus® II software supports various types of design entry and includes advanced integrated synthesis. The software also offers schematic netlist viewers that you can use to analyze a design's structure and see how the software interpreted your design. For additional information on design and coding guidelines, Quartus II integrated synthesis, and netlist viewers, see:
For a brief overview of design entry and synthesis features, refer to the Design Features and Synthesis product feature pages.
To search for known synthesis-related issues and technical support solutions (including design entry and netlist viewers), use Altera’s Knowledge Database. You can also visit the Altera® Forum to connect and discuss technical issues with other Altera users.
For further technical support, use mySupport to create, view, and update service requests.
Design and Coding Guidelines Resources
Table 1 provides links to available documentation on design and coding guidelines.
| Table 1. Design and Coding Guideline Documentation |
| Title |
Description |
| Design Planning with the Quartus II Software (PDF) |
This chapter of the Quartus II Development Software Handbook discusses important FPGA design planning issues, provides recommendations, and describes various tools available for Altera FPGAs to help you improve design productivity. |
| Design Recommendations for Altera Devices and the Quartus II Design Assistant (PDF) |
This chapter of the Quartus II Development Software Handbook describes synchronous design practices and recommended design techniques. It also describes the Quartus II design assistant that helps find potential design problems. |
| Recommended HDL Coding Styles (PDF) |
This chapter of the Quartus II Development Software Handbook provides Verilog HDL and VHDL coding style recommendations and examples, including inference of Altera megafunctions and device-specific coding guidelines. |
| Designing with Low-Level Primitives User Guide (PDF) |
This user guide describes low-level HDL design techniques using small architectural building blocks and assignments to specify a particular hardware implementation. |
|
Advanced Synthesis Cookbook: A Design Guide for Stratix II and Stratix III Devices (PDF)
Design Files (ZIP)
|
This user guide discusses hand-crafted “tricks” you can use to optimize design blocks for the adaptive logic modules (ALMs) in Stratix® II and Stratix III devices. The document includes a collection of circuit building blocks and related discussions, and each section includes a list of example design files that you can use for testing and to better understand the derivation of the more complex optimizations.
|
Table 2 provides links to available training and demonstrations on design and coding guidelines.
| Table 2. Design and Coding Guidelines Training and Demonstrations |
| Title |
Description |
Design Entry
(Online Demonstration) |
You will see how to set up a project and enter a design in the Quartus II software.
This is a 3.5-minute demonstration.
|
Design Planning Guidelines for High-Density FPGAs
(Online Course) |
You will learn how to avoid pin layout, power consumption, and timing issues with proper design planning techniques.
This is a 1-hour online course.
|
VHDL Basics
(Online Course) |
You will get an overview of the VHDL language and its use in programmable logic design.
This is a 1-hour online course.
|
Introduction to VHDL
(Instructor-Led Course) |
You will get a general introduction to the VHDL language and its use in programmable logic design. The emphasis is on the synthesis constructs of VHDL; however, you will also learn about the simulation constructs. You will gain a basic understanding of VHDL to enable you to begin creating your design. You will gain hands-on experience by implementing various simple but practical designs.
This is a 1-day instructor-led course.
|
Advanced VHDL Design Techniques
(Instructor-Led Course) |
You will learn efficient coding techniques for VHDL synthesis, particularly for Altera devices. You will gain experience writing behavioral and structural code and learn how to effectively code common logic functions including registered, memory, and arithmetic functions.
This is a 1-day instructor-led course.
|
Verilog HDL Basics
(Online Course) |
You will get an overview of the Verilog HDL language and its use in programmable logic design.
This is a 1-hour online course.
|
Introduction to Verilog HDL
(Instructor-Led Course) |
You will learn how to implement basic constructs and modeling structures in Verilog to create an optimal FPGA design. The emphasis is on the synthesis constructs of Verilog HDL; however, you will also learn about the simulation constructs. You will also learn how to take advantage of various features in Verilog HDL such as delays in programmable logic design. You will gain hands-on experience by implementing various simple but practical designs.
This is a 1-day instructor-led course.
|
Advanced Verilog HDL Design Techniques
(Instructor-Led Course) |
You will learn efficient coding techniques for writing synthesizable Verilog, particularly for Altera devices. You will gain experience in writing behavioral and structural code and implementing state machines with multiple efficient coding styles. You will also learn how to optimize a design to an FPGA.
This is a 1-day instructor-led course.
|
|
Using the Quartus II Software: Schematic Design
(Online Course)
Chinese Version: Using the Quartus II Software: Schematic Design
(Online Course)
|
You will learn how to use the Quartus II software graphic editor to create a schematic design. You will learn how to utilize the library of functions installed with the Quartus II software (e.g. multipliers, filters, etc.). You will also learn how to generate your own custom functions.
This is a 30-minute on-line course.
|
Integrated Synthesis Resources
Table 3 provides links to available documentation on Quartus II integrated synthesis.
| Table 3. Integrated Synthesis Documentation |
| Title |
Description |
| Quartus II Integrated Synthesis (PDF) |
This chapter of the Quartus II Development Software Handbook documents the design flow and language support in the Quartus II software. It explains how to improve and control your synthesis results with Quartus II synthesis options, attributes, and other features. It also discusses node-naming conventions and how to preserve nodes through synthesis. |
Table 4 provides links to available training and demonstrations on Quartus II integrated synthesis.
| Table 4. Integrated Synthesis Training and Demonstrations |
| Title |
Description |
Compilation
(Online Demonstration) |
You will see how to make settings in a project, start a compilation, and view your results.
This is a 2.5-minute demonstration.
|
Using the Quartus II Software: An Introduction
(Online Course) |
You will become familiar with the basic Quartus II design environment. You will learn about the steps of the basic FPGA design flow and how to use Quartus II software in the flow. You will locate basic functions in the Quartus II software user interface, such as where to create new projects and how to make pin assignments, and where to locate Quartus II software compilation output information.
This is a 1.5-hour online course.
|
The Quartus II Software Interactive Tutorial
(Online Tutorial) |
This interactive tutorial teaches you the basic components of the Quartus II design software including best-practice design flows, project management and design tools, and programming a device with your tested design. Each tutorial module has a Show Me, Guide Me, & Test Me component to first achieve an understanding of a design feature and then test you on what you have learned. You can navigate to any module in the tutorial at any time with the Table of Contents and explore features at your own pace.
This is a 4-hour online interactive tutorial course.
|
The Quartus II Software Design Series: Foundation
(Instructor-Led Course)
The Quartus II Software Design Series: Foundation
(Online Course)
|
You will create a new project, enter in new or existing design files, compile, and configure your device using the programmer to see the design working in-system. You will also enter basic internal and I/O timing constraints and analyze a design for these timing constraints using the TimeQuest timing analyzer. You will also learn how to plan and manage pin assignments and will discover how the software interfaces with common EDA tools used for synthesis and simulation.
This is a 1-day instructor-led course or 8-hour online course.
|
|
The Quartus II Software Design Series: Optimization (Instructor-Led Course)
|
You will learn advanced features of the Quartus II software that enable you to shorten your design cycle as well as improve your design performance and utilization. You will obtain your design goals in the area of performance, resource usage, and power consumption by using design strategies, HDL coding styles, and Quartus II software settings. You will also learn how to manage compilation times effectively.
This is a 1-day instructor-led course.
|
Netlist Viewers Resources
Table 5 provides a link to available documentation on the Quartus II netlist viewers.
| Table 5. Netlist Viewers Documentation |
| Resource |
Description |
| Analyzing Designs with Quartus II Netlist Viewers (PDF) |
This chapter of the Quartus II Development Software Handbook describes the user interface and features of the viewers and provides examples. The Quartus II RTL viewer, state machine viewer, and technology map viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, or constraint entry process. |
Table 6 provides links to available training and demonstrations on the Quartus II netlist viewers.
|
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