Release Notes For ModelSim Altera 6.5b May 21 2009 Copyright 1991-2009 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information. TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. The following are trademarks of of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal Spy. A current list of Mentor Graphics trademarks may be viewed at www.mentor.com/terms_conditions/trademarks.cfm. End-User License Agreement: You can print a copy of the End-User License Agreement from: www.mentor.com/terms_conditions/enduser.cfm. ______________________________________________________________________ Product Installation and Licensing Information For brief instructions about product installation please visit the "install_notes" file in www.model.com. The install_notes file can be viewed at: [1]http://www.model.com/products/release.asp For detailed information about product installation and licensing see the ModelSim Start Here Guide. The manual can be downloaded from: [2]http://www.model.com/support/documentation.asp Release Notes Archives For release notes of previous versions visit the release notes archive at: [3]http://www.model.com/support/default.asp or find them in the installed modeltech tree in /docs/rlsnotes How to get Support ModelSim Altera is supported by Altera Corporation * World-Wide-Web Support [4]http://www.altera.com/mySupport ______________________________________________________________________ Index to Release Notes [5]Key Information [6]User Interface Defects Repaired in 6.5b [7]Verilog Defects Repaired in 6.5b [8]PLI Defects Repaired in 6.5b [9]VHDL Defects Repaired in 6.5b [10]FLI Defects Repaired in 6.5b [11]VITAL Defects Repaired in 6.5b [12]SystemC Defects Repaired in 6.5b [13]Assertion Defects Repaired in 6.5b [14]Mixed Language Defects Repaired in 6.5b [15]Coverage Defects Repaired in 6.5b [16]General Defects Repaired in 6.5b [17]Mentor Graphics DRs Repaired in 6.5b [18]Known Defects in 6.5b [19]Product Changes to 6.5b [20]New Features Added to 6.5b ______________________________________________________________________ Key Information * The following lists the supported platforms: + win32aloem - Windows XP, Vista + sunos5aloem - Solaris 8, 9, 10 + linuxaloem - RedHat 9 and higher, RedHat Enterprise Linux 3, 4 and 5, SUSE Linux Enterprise Server 9.0, 9.1 and 10. ______________________________________________________________________ User Interface Defects Repaired in 6.5b * Dragging the wave slider could cause a crash. The problem has been fixed. * The help menu and toolbar fails to access the HTML documents on the Windows platform. This issue has been fixed. * Extremely long dataset names (> 80 characters) could cause a crash when a virtual signal was created. * The simulator could crash if waveform comparison was done on SystemVerilog string variables. This has been corrected. * When using Codelink or any design that adds items to the design structure via an FLI call during simulation, the U/I may crash if the Objects window Value column is set as the sort column. This issue has been resolved. * The Restart dialog would fail to appear if you tried to open it from an undocked window with the main session window iconified. This has been fixed. * Analog formatted waveforms could lose their min/max settings following a restart. This problem has been fixed. * An error could cause waveforms of busy signals to stick at the same value for an interval of time, zooming in would reveal the correct values. This error has been fixed. * Waveform compare failed for complex escaped identifiers in signal paths. * User defined radix did not work with hexadecimal numbers larger than 32-bits. This issue is now fixed. * The Verification Management Tracker window allows filtering which can be invoke with the "Filter" -> "Apply" menu. This menu did not work correctly in the "Tools" menu in the undocked window or the RMB popup menu after a second .ucdb file was opened. This has been fixed. * After clicking on an attribute value in the Verification Management Tracker window to edit it, if the user typed the escape key (to back out of rather than save any changes) an error resulted and the original value was lost. This has been fixed. * The Verification Management Tracker window could not cope with spaces in the names of attributes and therefore in the column header names. It used only the first word of the name and also muddled the column data. This has been fixed. * Loading source object database performance has been enhanced. * The parsing of the argument file by using the -f command line option behaves differently when called from shell prompt vs. the vsim prompt. This issue is now fixed. * Several of the CLI coverage commands, coverage tag, coverage analyze, coverage clear, and coverage unlinked, used the option -recurse instead of -recursive in at least one of: 1. the reference manual, 2. the command completion help in the GUI, 3. the usage message, or 4. the parsing of the command. Now -recursive is used consistently throughout for all of the CLI coverage commands. * Using an invalid option with the coverage clear CLI command (example: coverage clear -bogus) caused a crash. This has been fixed. * The U/I will loose keyboard focus, appearing to be unresponsive, until the focus is directed to another application and back again. This will happen when a window pane is close, and possibly under other conditions. This issue has been resolved. * Nologging any Verilog signal with WLF threads enabled could result in a crash. The problem showed up for a customer logging with: log -r /*; nolog -all The error has been corrected. * The display of signals when zoomed out was sometimes incorrect. The correct view would appear after zooming in. The problem has been corrected. * A signal was displayed incorrectly when zoomed out, showing a gap of no activity where the signal was active. Zooming in showed the correct view. The error has been corrected. * Verilog arrays of nets were sometimes displayed incorrectly in the Wave window. After an interval of time, the display would show the values for the array elements as 'X' even though new values had been set. The error has been fixed. * Creating a Wave window group using the wave group command or the wave group dialog did not preserve the properties (e.g. color, radix, etc.) on the signals being grouped. * Several Wave window group height related issues have been resolved including: + group item height changing on restart, + height switch on add wave command not working for groups, + grouping of objects of different height could cause the height of the group item to be incorrect. * Several Wave window group issues regarding nested groups have been addressed including: + deleting a nested group caused parent group failure, + not being able to create a group containing selected groups using the popup "Group..." menu selection, + not being able to create nested groups with the wave group command, + creating a nested wave group would always put the new group at the end of the parent group. + ungrouping a nested group would destabilize the parent group. ______________________________________________________________________ Verilog Defects Repaired in 6.5b * A module description starting within a `include file, but completed after returning from the `include, would sometimes associate a wrong or non-existent source file with subsequent declarations. This would sometimes be exhibited by a vopt internal error: ** Error: name.v(12): Internal error: ../../../src/vlog/vl_cpyidl.c(262) obj < maxFiles * Support for the -source option to the Verilog compiler and/or vopt would neglect to close files when consecutive errors occurred within the same file, but on subsequently decreasing line numbers. Eventually, the compiler might exit with an error message similar to: ** Error: (vopt-7) Failed to open file "filename" in w+ mode. Too many open files. (errno = EMFILE) * vlog's -E switch would incorrectly write tabs as '\t' to the output file. * Use of +nospecify on the vsim command line with optimized gate-level cells could crash the simulation. * An event on a class variable could result in a memory leak. This problem started occurring in 6.5 and is now fixed in 6.5b. * Loading multiple instances of the same design unit in Verilog and using a Verilog configuration or `uselib to specify one of the instances be a different type of design unit could cause a crash, unexpected errors, or unexpected simulation results depending on the type of design unit. Specifying a VHDL design unit when a Verilog module is expected or specifying a Verilog design unit when VHDL is expected would cause a crash. Specifying a UDP in place of a module could cause unexpected errors for port connectivity. Specifying a program block when a module was expected could cause statements executing in the module instances to execute in the reactive region. * Fixed spurious error about X or Z values during randomization of 2-state enumerated type variables. * Detected loading error #3609 for forward hierarchical reference to optimized cell port from SystemVerilog interface. * When three or more bind packages are specified on the vsim command line, vsim will hang. This issue has been resolved. * The simulator had incorrectly set real values to zero on implicit conversion in Verilog simulations. * In some cases involving sign extension, generate condition or loop conditions could be evaluated incorrectly for optimized designs. * After an Iteration Limit was reached due to a zero-delay oscillation, simulation stopped with an error. * While parsing external constraint for a class that is extended from a parameterized class, vlog used to give the wrong error message "Invalid scope specified for constraint block". This error is now fixed. * In some cases events triggered by changes to a SystemVerilog class property failed to execute the waiting code. * Event controls and wait statements on automatic variables inside a fork block would sometimes fail to activate the waiting code. * Connecting a SystemVerilog port of type real with a SystemVerilog variable of type int would pass incorrect (junk) values. This has been fixed. * vopt would error out with an incorrect "Failed to find in hierarchical name" error when the SystemVerilog bind construct was used to bind to a module instantiated inside black boxed regions. This has been fixed. * vsim would produce an incorrect "Unresolved reference to .*" error when binding to an instance inside a black-boxed region using the SystemVerilog bind construct. This has been fixed. * Using a SystemVerilog break or continue statement inside a repeat loop with a constant repeat count of 1 caused a fatal error during the simulation run. * Using a virtual interface type as a type parameter on a module instantiation caused vopt to crash with a segmentation fault. * Using array query functions like $left, $right, $high, $low or $bits on fixed-sized arrays of dynamically sized objects incorrectly reported an error when used in a constant expression. * Fixed false error involving ext. refs. to elements of modports through a virtual interface. * Hierarchical references into signals in a clocking block would sometimes cause vopt to crash. * A non-blocking assignment to a field select of an array element where the type of the variable is a parameter type and there is also an assignment to the array index in the same time step may produce incorrect results. * In certain cases vopt would produce a segmentation violation when coverage was enabled. * Certain kinds of non-blocking assignments where the left hand side of the assignment contains a part select, bit select, array index, and/or field select may create a process that causes a crash if the user interface queries for a list of active processes between the time when the NBA is scheduled and the time the NBA is executed. * Certain cases might have produced the wrong results for case statements where the number of Case Clauses is less than 2. This has now been fixed. * Extended VCD did not consider the contribution of specify path drivers. * The vopt command sometimes reported the error "Failed to find 'super' in hierarchical name." incorrectly for static method calls that should have resolved into a super class. * Declaring a parameter inside a class body and using that parameter to declare a type could cause vsim to crash during elaboration in the -novopt flow. This crash did not occur for parameterized classes declared like: "class C #(...parameter list...)" * Always_comb sensitivity was not being computed correctly for external references with indexed names. ______________________________________________________________________ PLI Defects Repaired in 6.5b ______________________________________________________________________ VHDL Defects Repaired in 6.5b * If a named association in a port map is partially associated to OPEN, then if the open subelement is a slice or record, elaboration would cause a crash. * In the non-vopt flow compiled SDF annotator could not resolve instances under VHDL generate blocks. Therefore, SDF annotations targeted to such instances failed. * Running vcom or vopt with Finite State Machine detection enabled (+acc or +acc=f) on Windows platforms would sometimes result in an error message like: # ** Fatal: Unexpected signal: 11. * If a process is stopped in a subprogram with signal parameters, the simulator could crash while trying to get information on the signal parameter to display in the GUI. * If SDF is applied to a design containing VHDL, the values of record type generics may become corrupt. Additionally, the tool may report the error: Defparam iteration limit of 10 exceeded. * Package standard functions to_bstring, to_binary_string, to_octal_string and to_hex_string were visible regardless of what VHDL language version was used. This caused potential conflicts with same named subprograms declared in other packages. Now these names are only visible when language version VHDL2008 is used. * The -check_synthesis option warning message #1400 could sometimes report the incorrect file name when vcom was invoked with more than one file name on its command line. * A suite of -lint messages for vcom has been implemented. These assist in pointing out some potential simulation errors. Message #1292 occurs when the prefix of a slice name has an unknown index range direction (such as, but not limited to, when the prefix is of an unconstrained array type) and the discrete range of the slice has a known direction. Message #1298 occurs when the prefix of a slice name is of an unconstrained array type and the discrete range of the slice is locally static. Message #1293 occurs when the prefix of an indexed name is of an unconstrained array type and an index value is locally static. * In some cases when a constant vector is driving an input port whose dimensions are defined using a generic, vsim may fail giving an invalid operand kind error. This is now fixed. ______________________________________________________________________ FLI Defects Repaired in 6.5b ______________________________________________________________________ VITAL Defects Repaired in 6.5b ______________________________________________________________________ SystemC Defects Repaired in 6.5b * The -sc_arg vsim command line option takes the argument that follows it on the command line and makes it available for access within the user's SystemC code. Some vsim command line options, notably -f, -h, and -l, could not be passed with the -sc_arg option. Instead, they were interpreted as options to vsim and were not accessible from SystemC. This has been fixed. * Logging SystemC structures containing float types could sometimes cause a crash on the Solaris platform. * Fixed scparse-gcc error for ambiguous "+=". ______________________________________________________________________ Assertion Defects Repaired in 6.5b * Implemented some performance improvements in the assertion browser GUI for designs with a large number of assertion instances. This was done mainly for the browser's flat mode, not the hierarchical mode. ______________________________________________________________________ Mixed Language Defects Repaired in 6.5b * If a Verilog or SystemVerilog module that instantiates a VHDL design unit is place through use of the SystemVerilog bind statement, the design would fail to elaborate and crash. * A Verilog parameter of vector type would sometimes produce an incorrect error message in vopt saying "generic type mismatch" when connected to a VHDL generic of integer type. This was only for cases where VHDL instantiates Verilog and has been fixed now. * VHDL resolved subtypes of record were not correctly handled in scgenmod and gen_xml utility. This has been fixed. * SignalSpy would give an incorrect type mismatch error with single width VHDL vectors (e.g. 4 to 4) as source and single width Verilog vectors (like [0:0]) as destination. This has been fixed. * scgenmod would generate an incorrect error saying 'unsupported type' for VHDL 'unsigned' datatypes. This has been fixed. * Wrong values were propagated while using init signal_driver/init_signal_spy when the source object was a bit-select of a packed Verilog vector. This has been fixed. * When incremental flow was used and there were multiple ports in the bound Verilog module with the same case-insensitive name (e.g. hdl_sig and HDL_Sig), port binding would be incorrect when binding to a VHDL target scope using the SystemVerilog bind construct. If the type of these ports were different then an incorrect error message would be received for a type-mismatch. But when these ports were of the same type, wrong port-connections would sometimes be made silently. This has been fixed and now the port connections are always correct for such cases. * Binding a Verilog module/program instance to a specific instance of a VHDL target using the SystemVerilog bind construct would not work when the bind_target_instance identifier resolves to both an instance name and a module name. An example of such usage is: bind sub:sub_inst assertmod inst1(); * vsim would propagate incorrect values when the SystemVerilog bind construct was used for binding Verilog with VHDL and VHDL integer generics were overridden with real values. This has been fixed and now an error message will be issued for such cases. * When the SystemVerilog bind construct is used to bind Verilog to VHDL target scopes, vsim would sometimes report an incorrect "incompatible mode" error for inout ports when invoked with the -novopt. This has been fixed. * The wildcard pattern ".*" used with port connections did not work at the SystemVerilog-VHDL mixed language boundary when mixed with other named connections. This has been fixed. * For SystemVerilog instantiating VHDL, generics of type string would acquire incorrect values when overridden with SystemVerilog parameters of type string. This has been fixed. * scgenmod would exit with a segmentation fault when invoked with the -s command-line option on a VHDL entity containing a port of type 'time'. This has been fixed. * Connecting an input port in the bound SystemVerilog module with an output port of the target VHDL would not work while binding to VHDL target scopes using the SystemVerilog bind construct when port actual expressions contained hierarchical references. This has been fixed. * A Verilog port of packed vector type (of bit, reg or logic) having negative bound(s) would produce an incorrect error message in vopt when connected to a VHDL port of equivalent type. This was only for cases where VHDL instantiates Verilog and has been fixed. ______________________________________________________________________ Coverage Defects Repaired in 6.5b * Fixed a Tcl stacktrace error when a design is loaded in the simulation GUI in coverage mode which is not compiled with code coverage options. * Fixed a merge warning message for weight mismatch in merging regular instances with installed instances. * vcover merged did not allow installed paths without the leading path separator. * Test tracker showed that the testplan section was linked when it was not. This has been fixed. * Source code is annotated to HTML reports even if the -nosource argument is passed to the coverage/vcover report command. This has been fixed. * Toggle coverage for packed fixed-size arrays was not reported correctly. This has been fixed. * Coverage pragma 'toggle_ignore' would not exclude variables inside SystemVerilog interfaces. This has been fixed. * vlog/vcom would silently ignore incorrect usage of coverage pragmas. This has been fixed and a warning message will now be issued whenever a coverage pragma is used outside design unit scope. * When focused expression coverage finds more rows in an expression/condition than the maximum limit, the warning issued would report incorrect number of rows that the expression needs. This has been fixed. * Command line options -nocovershort and -covershort were incorrectly being handled by vsim. These options are only applicable for vlog, vcom and vopt. This has been fixed. * Toggle counts in the Object window would ignore 'countlimit' and continue to increment beyond this limit. This has been fixed. * The UDP truth table for expressions containing "nand" and "nor" operators was incorrect. This has been fixed. * When compiled with -coverExcludeDefault, statements inside the default block were not excluded. This has been fixed. * Some additional constructs have been supported to make toggle coverage pragmas more flexible and user friendly. Here are the three constructs that are supported: /* Using all without the double quotes. */ //coverage toggle_ignore sig_arr all /* Specifying list without double quotes. */ //coverage toggle_ignore sig_arr 1 4-5 /* Omitting the word all to implicitly imply excluding all bits. */ //coverage toggle_ignore sig_arr * Excluding individual SystemVerilog and VHDL enum elements using the toggle add -exclude command was broken. This has been fixed. * Verilog expressions containing single-bit vectors (like 'opcode[0:0] | opcode[7:7]') as operands would sometimes evaluate to incorrect values when the values of these operands were 'z'. This would only happen when code coverage was enabled, and has been fixed. * Multi-dimensional fixed-size packed Verilog arrays were not being considered for toggle coverage. This has been fixed. * Toggle coverage reports would incorrectly show single dimensional unpacked wire arrays as single toggle nodes. This has been fixed. * Multi-dimensional array elements would incorrectly appear as single-dimensional array elements in the FEC reports. This has been fixed. * Toggle coverage would not count 0->X->1 and 1->X->0 as valid transitions. This has been fixed. * SystemVerilog unpacked structures were not being automatically included for toggle coverage when the design was compiled using +cover=t and vsim was invoked with -coverage command-line option. This has been fixed. * Toggle coverage reports would show the number of counts of a real variable under the 'Toggled' column instead of the 'Count' column. This has been fixed. * Statement coverage reports would incorrectly show statements containing class headers and endclass as excluded by pragma, even when there was no active coverage pragma in the file. This has been fixed. * The Source window showed the exclusion icon on the "case" line in viewcov mode. It's now the same as live simulation mode where the exclusion icons are shown only on the case item lines. * The number of active case items in the Missed Branch window did not reflect the fact that some case items of a case branch are excluded. * The expression and condition report summary lines in the Details window were not consistent for UDP and FEC rows when all rows are excluded. * The Total Coverage and Assertions columns were empty in the Structure window when coverage in under VHDL architecture. * The excluded coverage items are now marked as "E-hit" in details text report when items are hit (having nonzero count). This is the default behavior now. The option -noexcludedhits is added in coverage text report to disable the showing of excluded hits. ______________________________________________________________________ General Defects Repaired in 6.5b * It was possible to specify a target file for vencrypt that would match a source file which caused the source file to be overwritten. A read only source file would cause a crash. * For some designs, vsim could not load a vopt design which referenced -archive libraries. * sdfcomp errors when the working library is undefined or unwritable because the sdfcomp output file can not be created. ______________________________________________________________________ Mentor Graphics DRs Repaired in 6.5b * dts0100362733 - Support for array reduction functions ( esp sum() ) and "with" statements to bi-directional constraints in SV. * dts0100401884 - Lack of documentation on running in batch mode. * dts0100544835 - VHDL Generic to Verilog parameter binding without foldable values. * dts0100545367 - Analog format loses min/max values after a restart. * dts0100568827 - Enhance force to list signals forced by force_signal(). * dts0100573768 - Prevent port collapsing in Verilog for VCD output. * dts0100579170 - Wave window crash when working in the Wave window during a run. * dts0100579336 - An event on a class variable could result in a memory leak. * dts0100579998 - vsim -view crashes when the WLF file has a long name. * dts0100580446 - Source window does not reflect results of coverage exclusions. * dts0100581012 - Difference between the behavior of vopt and novopt for Verilog configurations. * dts0100581300 - When I dock the wave window and then undock it, it does not remember it's original size. * dts0100575931 - vopt crashes when module binding with code coverage enabled. * dts0100581743 - Multiple bind packages hang vsim in novopt mode. * dts0100582234 - Waveforms appear to have gaps that display no activity. * dts0100583594 - Restart dialog does not appear when main application is minimized. * dts0100583787 - User defined radix did not work with hexadecimal numbers larger than 32-bits. * dts0100584644 - Crash at simulation due to sort Value column in the Objects window. * dts0100585677 - Bad NBA code generated for LHS containing index into parameterized array of record type. * dts0100585990 - Compiler reports error message against wrong source file. * dts0100586566 - Fatal error received # ** Fatal: (SIGSEGV) Bad handle or reference. * dts0100584979 - Big lag time in 6.5/6.5a in loading source object database compared to 6.3f. * dts0100584880 - Inconsistent parsing of the argument file. * dts0100583147 - Optimization does not work with modport in a SystemVerilog design. * dts0100524086 - Pass a real to an integer parameter in binding. * dts0100572093 - Bind with hierarchical signal path to VHDL. * dts0100534129 - The number of FEC rows reported in the warning message does not match the total number. * dts0100503870 - coverExcudeDefault switch doesn't work correctly. * dts0100533590 - When compiling with -coverExcludeDefault, it doesn't exclude the statements following the 'when others=>' line. * dts0100427260 - Add new toggle coverage stats. * dts0100585855 - sdfcom errors when loading into vsim 6.5a and no work library exists. * dts0100585800 - ** Fatal: (SIGSEGV) Bad handle of reference. * dts0100586932 - Internal error in vopt due to virtual interface type parameter. * dts0100588024 - WLF file displays incorrect values. * dts0100543992 - Cannot create parent group for selected groups in Wave window. * dts0100241614 - Request checker to check and report if a code coverage hit occurred even though it had been excluded. * dts0100585649 - Problem with unique case. * dts0100586886 - Direction in eVCD file generated by vsim is wrong. * dts0100568912 - Parameter in class causes crash with -novopt. * dts0100585125 - always_comb implicit sensitivity list is incorrect in novopt. ______________________________________________________________________ Known Defects in 6.5b * On Windows platform, If Destructor breakpoint on SystemC object is set via command "bp -c < function_name >", Debugger sometimes does not stop at the breakpoint. * On Windows platform, if breakpoint is set on a SystemC object destructor, Debugger sometimes crashes while quitting simulation. This crash can be avoided by setting env variable SC_NO_LIB_UNLOAD, which will prevent unloading of the shared library. * The simulator will hang if it tries to create a WLF file while running on a Linux 64-bit operating system from a working directory which does not support large files. One common instance of this is executing an add wave command, when the working directory was created under an older 32-bit Linux OS. This is a Linux operating system bug and cannot be fixed by the simulator. A workaround for release 6.3 and above is to execute the simulator with command line option -wlfnolock. * The stack unwinder on the linux_x86_64 OS is unreliable. The unwinder is the fundamental facility provided by the OS for sampling where program execution is at. The unwinder is necessary for gathering performance data. This is a known issue with this specific OS and is why performance data will be incorrect or non-existent on this platform. * Users should be mindful of enabling both performance profiling and memory profiling at the same time. Memory profiling requires much overhead process, and it can skew the results of the performance profiling data. * On certain (RedHat) Linux Operating System versions the "-restore" feature occasionally fails. This is due to the memory allocation security (anti-hacking) feature of Linux. RedHat Enterprise release v.3 update3 was the first version to have this security feature. In these Linux releases two consecutive program invocations do not get the same memory allocation foot-print. For the "-restore" feature the simulator relies on having the same memory allocation foot-print. Users are advised to re-try this feature a few times as on average 3 out of 5 attempts are successful. In recent Linux versions, an override for this anti-hacking feature is provided. Please use it at your own discretion. * In code coverage, there is no way to exclude a condition or expression table row for the case of more than one table on a line and the table in question is not the first table on the line. * Support of debugging C code during a quit command was disabled on Windows. The corresponding C Debug command cdbg stop_on_quit was also disabled on Windows. * Specparams can be learned during the learn flow, but cannot be found on consumption. The workaround is to use full +acc deoptimization. * On Red Hat Enterprise Linux release 5 platform, If SIGSEGV signal occurs during the simulation and if CDEBUG is on, C-debugger traps the signal, and when continued, vsim gets terminated right away, instead of exiting with proper error status. * If you have code coverage on in VHDL and get the following sort of warning: # Loading mypackage(body) # Internal Warning in process_sub: failed to find local inlined subprogram called in pkg # (mypackage ); flags 7 filenum 0 lineno 241 tokno 2 # Disabling code coverage for this inlined subprogram Then add the -noFunctionInline option to vcom for that package, or reorder the subprograms in the package body to be defined before they are used. * Code coverage is now giving results for SystemVerilog nested modules, interfaces and program blocks. One remaining issue is that if a nested module has more than one instance, only one of the instances will show code coverage data, and the data therein will be the sum of all the instances of that module. This will be improved in a later release. * The vpiPorts iteration on vpiEnumNet, vpiIntegerNet, and vpiStructNet VPI objects has been disabled as it was incomplete and unsafe to use. ______________________________________________________________________ Product Changes to 6.5b * The breakpoint behavior of the -cond option has changed to re-parse expressions each time the breakpoint is hit. This allows expressions with local references to work. Note that because of this change, condition expressions referencing items outside the context of the breakpoint must use absolute names. This is different from the previous behavior where a relative signal name would be resolved at the time the bp command was issued, allowing the breakpoint to work even though the relative signal name was inappropriate when the breakpoint is hit. * Errors involving assignments to enums in vlog, vopt, or vsim are now printed using message #8386, which is suppressible. * In previous versions of the simulator, a random seed was sometimes assigned to processes created for non-blocking-assignments, and this could affect random-stability, depending on optimizations that were in effect. In 6.5, this is no longer the case; but it may result in different results involving randomization from 6.4x. * FSM recognition reporting in the coverage FSM flow has been made consistent with the FSMDEBUG flow. Both flows will only dump the number of FSMs detected by default. The -fsmverbose option can be used to display FSM RECOGNITION INFO, if required. * The default keyboard shortcuts for the cut/copy/paste operations have been changed to match the Windows standard of Control-X/C/V respectively. A new preference setting (Main/PCEditBindingsOnUnix) category has been added to control this. Note, any opened text windows at the time the preference is changed will not see the change until the next time the GUI is started. * A new search capability has been added for all windows that previously supported use of the Contains toolbar and/or the "Edit > Find..." menu. This new "Search Bar" will appear along the bottom edge of the window it's being used from. It completely replaces the old Contains toolbar and individual Find dialog boxes. For those windows that support both filtering and finding, the mode for the Search Bar would need to be set accordingly (the last selected mode for the Search Bar is remembered between sessions). The various ways of choosing the mode are: + use Control+M while the Search Bar has the keyboard focus + select the mode from the Search Bar's menu (located on icon at far left) + click the label text which indicates the current mode The current mode of the Search Bar is displayed as a text label to the left of the type-in field, as well as by the icon located at the left edge of the type-in area. The main benefit of having the filtering functionality within the Search Bars is that each window now has its own unique type-in field as opposed to having to share the common Contains toolbar. The latter could lead to confusion over what is shown in the toolbar and the filtered content of the windows. There is also a simple history mechanism to allow saving search strings for later use. The keyboard shortcuts to support this are: + Control+S -- save current search text into history list + Control+P -- retrieve previous search text + Control+N -- retrieve next search text * You must now change the encoding of your character representations with the encoding system command, where the syntax is: encoding system To obtain a complete list of options, use the encoding names command with no arguments. Previously you could perform this action with the View > Encoding menu, which has been removed. * The VPI compatibility for this release defaults to the 2009 IEEE 1800 standard. This introduces, among other things, new VPI types for packed arrays of struct nets and struct variables. Normative files vpi_user.h, sv_vpi_user.h and vpi_compatibility.h are supplied with the latest known standardized contents. Users should however be aware that at the time of release the IEEE 1800-2009 was not complete. * Event order differences between an optimized and unoptimized design have been reduced with this release. Specifically, event propagation through Verilog zero-delay continuous assignment and primitive networks has been changed such that optimizations involving these networks are much less likely to result in behavioral differences. However, note that a design depending on the old event ordering may not behave the same with this release. Both, the unoptimized and optimized behavior may change, but should match each other more closely. Ideally, "races" should be removed from the design, but, if desired, the user may revert back to the old event ordering by specifying the -noimmedca vsim option or by setting the following line in the modelsim.ini file: ImmediateContinuousAssign = 0 * Code coverage information is no longer saved under design units in UCDB files. Instead, code coverage data for design units are constructed on-the-fly when a UCDB file is opened in IN_MEMORY mode. The information is constructed by merging all code coverage data from instances in the UCDB into the corresponding design unit. This has two main implications for UCDB API users: 1. Using APIs to create code coverage data under design units is not allowed anymore and the API calls will error out. 2. Opening UCDB files in read-streaming mode will not generate callbacks under design units since there is no code coverage data anymore. * The PrefMain(ShowFilePane) preference is now obsolete. The Files pane will follow current layout as do all other windows. * The view * command is now obsolete. The argument "*" will be ignored with no note warning or error. A window name or window name prefix must be supplied in order to open or configure any windows. * When a non-existent entry of an associative array is read, a default value is returned. We now re-initialize that value each time, in case the user modified it. The exception is if the user set an explicit default value. For example: integer bar[integer][$]; // Assoc. array of queues. task execute(); // Below, bar[2] doesn't exist, so we return the default value, // an empty queue. The user is pushing 777 onto it. bar[2].push_back(777); // Referencing bar[2] again now returns an empty queue. In previous // versions, we returned {777}. The $display now prints 'x'. $display ("bar [2][0] = %0d", bar[2][0]); * Some changes have been made to toggle coverage specific vsim command-line options. + The -togglevlogints option has been removed as SystemVerilog integer types are now supported for toggle coverage by default. + The following vsim command-line options have been changed as they were inconsistent with our convention. o -togglenoints CHANGED TO -notoggleints o -togglenovlogints CHANGED TO -notogglevlogints * We now treat a slice of a string as a string. This seems obvious, but it is not described anywhere in the LRM. The following is now supported: string line = "Hello there"; string targ; initial targ = line[0:5]; * The option -fsmdebug has been deprecated. A new letter code 'f' has been added to +acc to enable FSM detection and debugging. This also makes it possible to have module and instance bases selection with FSM debug. +acc without any letter code with automatically enable +acc=f. * Conditional timing check expressions are displayed as they appear in the HDL description. In the past equivalent conditions were displayed. For example: &&& (cond === 0) was displayed as &&& (~cond) * In some cases the -vmake flag will be required to correctly capture Verilog source file dependencies. * Invalid vsim command line switches used with -load_elab will now by default generate a warning message and not an error message. The warning message has a Message Id associated with it and is thus suppressible. ______________________________________________________________________ New Features Added to 6.5b * Verilog port direction is not enforced by the language or tools. For this reason VCD dumpports uses the location of the drivers on the net to determine whether the value being dumped is input or output. A new option, -force_direction, has been added to force dumpports to use the specified port direction and not driver location to determine direction. * In constraints, array reduction methods with the "with" clause were not supported (e.g. arr.sum() with (int'(item)) == 12;). Now, this support has been added. * The command force, without any options, produces a list of existing forces. The forces listed were only forces that occurred due to prior force commands. This listing behavior has been enhanced to also list forces coming from the Signal Spy signal_force()/$signal_force() calls from within VHDL/Verilog source code. * The extraction parameter "searchpath" is added to the xml2ucdb utility (command-line option -searchpath) to specify one or more directories to be searched by xml2ucdb looking for test plans' XML files. The option allows directory searching for nested test plans defined in the XML to be set on the command line and within the ini file. This then allows the testplan to be just a filename. * The vlog command now has a new switch -novtblfixup that affects the behavior of virtual method calls in SystemVerilog class constructors. By default, while a constructor is executing the this reference is treated as if it is a handle to the type of the active new() method which implies that virtual method calls resolve will not execute methods of an uninitialized class type. With -novtblfixup the type of this does not change during construction, and virtual method calls behave as they would in normal class methods. * vdir -l will now display the start location of a design unit. The location is displayed in the form :. * A new option -modelsimini /path/to/modelsim.ini has been added to vsim, vcom, vlog, vopt, sccom, scgenmod, vgencomp, vmap, vdir, vdel, vmake, vcover, sm_entity and hm_entity. The default ini settings would be set using the file specified with the option.