Altera® Quartus® II software includes a wide range of features to help you optimize your design for area and timing. This page provides resources to help you with:
Design Optimization
Design optimization can help you improve performance to close timing, reduce resource usage, and reduce compilation times. Table 1 lists the support resources for design optimization.
| Table 1. Design Optimization Support Resources | |
| Resource | Description |
|---|---|
| Area & Timing Optimization (PDF) | Chapter of the Quartus II Handbook. Explains techniques to reduce resource usage, improve timing performance, and reduce compilation times when designing for Altera devices. |
| Optimization Advisor | Describes how the Quartus II optimization advisors can guide you to improve timing and resource usage. |
| LogicLock® Design Methodology (PDF) | Chapter of the Quartus II Handbook. Describes how you can use LogicLock regions to control logic placement. |
| Timing Closure Floorplan (PDF) | Chapter of the Quartus II Handbook. Describes how you can use the Timing Closure Floorplan to analyze your design fitting results, as well as make location assignments. |
| Design Guidelines for HardCopy® Stratix® Performance Improvement (PDF) | Chapter of the HardCopy Series Handbook. Describes how to optimize HardCopy Stratix-based designs. |
Quartus II Design Entry and Synthesis Support Resources page sections:
|
Lists Quartus II incremental compilation and design and HDL coding resources.
Incremental compilation can be used to reduce compilation times and preserve results during optimization. Optimizing your design source code can be a powerful way of obtaining good quality of results. |
| Training Courses & Demonstrations | |
| Optimization Advisor (demo) | See a quick demonstration on Quartus II software's optimization advisor. |
| Designing with the Quartus II Software (instructor-led course) | Optimize FPGA usage by setting logic constraints, and improve FPGA performance by assigning timing constraints. You will also analyze Quartus II synthesis, placement, and routing, and make decisions to improve results. |
| Accelerating Design Cycles with Quartus II Software (instructor-led course) | Optimize and preserve logic performance using LogicLock regions, use the Quartus II incremental compilation flow to reduce compile times, and preserve performance on selected regions of your designs. Use the Design Space Explorer (DSE) to test Quartus II settings and select those that optimize your code for speed or area. You’ll also learn how to use Quartus II software's debugging features. |
| Using Quartus II: LogicLock Regions (online course) | Learn how to use the LogicLock feature to improve FPGA design performance, and see how the LogicLock feature can be used in hierarchical or team-based design flows to "lock" the performance and placement of design submodules, thus accelerating design cycles. |
Physical Synthesis
Quartus II software offers physical synthesis netlist optimization to optimize designs further than the standard compilation process. Physical Synthesis can help improve the performance of your design regardless of the synthesis tool used. Table 3 lists the support resources for physical synthesis.
| Table 3. Physical Synthesis Support Resources | |
| Resource | Description |
|---|---|
| Netlist Optimizations and Physical Synthesis (PDF) | Chapter of the Quartus II Handbook. Explains how the netlist optimizations and physical synthesis in Quartus II software can modify your design’s netlist and help improve your quality of results. |
Design Space Explorer
The Design Space Explorer (DSE) automates finding the set of options for best results in any individual design. DSE explores the design space of your design by applying various optimization techniques and analyzing the results. Table 4 lists the support resources for the DSE.
| Table 4. Design Space Explorer Support Resources | |
| Resource | Description |
|---|---|
| Design Space Explorer (PDF) | Chapter of the Quartus II Handbook. Describes the DSE and how you can use it to obtain the best compilation results. |
| Design Space Explorer Custom Space | Quartus II design example. Creating an optional custom space allows for full customization over the Quartus II options that DSE will explore. |
| Training Courses & Demonstrations | |
| Design Space Explorer (demo) | Get an overview of Quartus II software's DSE tool. |
| Accelerating Design Cycles with Quartus II Software (instructor-led course) | Learn to use incremental compilation, the LogicLock feature, Design Space Explorer, Chip Editor, SignalTap® II logic analyzer, and tool command language (TCL) scripts to shorten your design time and achieve optimal results. |
