Quartus II 仿真支持资源
Simulation is critical in verifying your design behavior. Simulation of designs written in HDL using a simulator and testbench is a proven technique to verify large designs. The Quartus® II design suite includes the Quartus II simulator and support for all the popular third-party simulators for functional and timing simulations.
Formal verification is a proven way to verify a design's implementation. Quartus II software supports popular third-party industry tools for formal verification.
For additional information on simulation, see the following:
For additional information on formal verification, see the following:
For a brief overview of the verification and simulation features of the Quartus II software, refer to the Verification and Simulation product feature page.
To search for known simulation and verification issues and technical support solutions, use Altera's Knowledge Database. You can also visit the Altera® Forum to connect and discuss technical issues with other Altera users.
For further technical support, use mySupport to create, view, and update service requests.
Simulation Resources
Table 1 provides links to available documentation for simulation.
| Table 1. Simulation Support Documentation |
| Resource |
Description |
| Quartus II Simulator (PDF) |
This detailed chapter in the Quartus II Development Software Handbook explains Quartus II simulator features and simulation flows for functional and timing simulation. |
|
Mentor Graphics ModelSim Support (PDF)
Synopsys VCS Support (PDF)
Cadence NC-Sim Support (PDF)
|
These comprehensive chapters from the Quartus II Development Software Handbook provide step-by-step instructions for performing functional register transfer level (RTL), functional post-synthesis, and post-fitting timing simulations with the Mentor Graphics ModelSim/ModelSim-Altera, Synopsys VCS, and Cadence NC-Sim simulation tools. |
| AN 340: Altera Software Licensing (PDF) |
This application note describes options for licensing Altera software and the three steps required to license it: obtain a license file, set it up, and specify the license location. This document also includes tips for troubleshooting licensing problems, answers to common questions about licensing, and detailed information about the format of Altera license files. |
| Simulating Altera IP in Third-Party Simulation Tools (PDF) |
Altera intellectual property (IP) provides a quick way to build your design without spending time on writing your own RTL for different components of the design. All Altera IP supports simulation in VHDL and Verilog. This chapter explains how to perform functional and gate-level simulation of Altera IP with third-party simulation tools. |
| AN 351: Simulating Nios II Embedded Processor Designs (PDF) |
This application note describes the process of setting up and running an RTL simulation in the ModelSim simulator using Nios® II design examples, SOPC Builder, and the Nios II integrated development environment (IDE). |
| Aldec Active-HDL Support |
This Aldec web page describes the Quartus II Active HDL simulation flow. It explains how to use the NativeLink feature in Quartus II software for simulating designs with the Aldec Active-HDL simulator. |
| ModelSim Command Reference (PDF) |
This command reference manual, developed by Mentor Graphics, describes all ModelSim commands. |
| ModelSim Tutorial (PDF) |
This tutorial, developed by Mentor Graphics, provides lessons on using the ModelSim simulator. |
Table 2 provides links to available training and demonstrations for simulation.
Formal Verification Resources
Table 3 provides links to available documentation for formal verification.
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