设计实例

设计实例指帮助您开始使用英特尔® FPGA 产品的 HDL 代码示例。所有实例都可作为您设计的起点,而且其中部分实例专为特定开发套件量身打造。现成的设计实例可提供高效的解决方案,帮助您解决设计问题。通过这些实例说明具体构建模块在系统设计中的使用。例如,针对 Stratix®、Arria® 和 Cyclone® FPGA 产品家族的各种外部内存控制器应用。您还可以从 应用说明 和户指南中找到其他相关设计实例。

SoC 设计实例是现成的软硬件项目,可作为评估和使用英特尔 SoC FPGA 特性的起点。 

设计输入或工具实例重点介绍了设计输入流程。它们包含演示基本逻辑块、脚本处理、门级时序仿真工具和调试等方面的实例。同时还包含有关 Quartus® Prime 软件功能的一些实例。如欲了解更多有关不同设计输入方法的信息,请参考 Quartus Prime 软件中的“帮助”文件。

有关 MAX® 10 FPGA 产品家族及其开发套件的设计请访问新的设计商店

Design Examples
Device Targeted Development Kits Supported Qsys Compliant Quartus II Version
Cyclone III
Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition
- 10.0
Design Examples
Device Targeted Development Kits Supported Qsys Compliant Quartus II Version
- - - 9.1
- - - -
- - - 9.1
- - - 7.1
- - - -
- - - -
Cyclone III , Stratix II
Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition, Nios II Development Kit, Stratix II Edition
- 9.0
Cyclone III
Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition
- 8.1
- - - -
Stratix II , Cyclone II
- - 9.0
- - - -
- - - 7.2
- - - -
Design Examples
Device Targeted Development Kits Supported Qsys Compliant Quartus II Version
- - - 7.2
- - - -

我们的 SoC 系列可在硬件性能、低功耗、外形和成本方面达到完美平衡。因为 SoC 集成了大量的硬核知识产权 (IP) 模块,因此可帮助您降低系统的整体成本和功耗,并缩短设计时间。

所提供的设计实例主要面向以下开发套件:

所有设计实例均带有设计档案和自述文件。相关设计的自述文件均包含设计档案导入、设计软件编译、可执行文件运行,以及预期的终端输入等方面的说明。

其他设计实例请访问SoC RTOS和HWLIBs 支持页面以及 Rocketboards.

Table 1: SoC Design Examples

Design Name Description File/Webpage Readme
SDMMC GSRD The Golden System Reference Design (GSRD) provides essential hardware and software system components that can be used as a starting point for various custom user designs. User Manual Arria 10 -
QSPI GSRD

Example

Arria 10

-
SGMI GSRD Release Notes Arria 10 -
NAND GSRD Coming Soon Coming Soon
Remote Update This project provides an example on how the user can remotely update the hardware and software running on an Altera Arria 10 SoC through a web interface.

Example

Arria 10

-
Remote Debug This example explains how to perform remote system debugging with the System-Level Debugging (SLD) tools.

Example

Arria 10

-
HPS-to-FPGA Bridges This design example exercises the memory mapped interfaces of the hard processor system (HPS) exposed to the FPGA fabric. The design performs memory tests by writing and reading the HPS memory using various ports of the HPS and measures the performance of the data movements.

Example

Readme-A10

Readme-CV

PCIe Root Port This reference design demonstrates a PCIe root port running on an Arria 10 SoC Development Kit connected to either a Cyclone V GT FPGA Development Kit PCIe end point or a generally available Intel PCIe Ethernet adapter card end point. It is also applicable on Cyclone V SoC Development Kit and Arria V SoC Development Kit.

Example

Arria 10

Arria V

Cyclone V

-
Secure Boot This document provides methods and design examples for implementing an Arria 10 SoC secure boot system using tools from the SoC Embedded Design Suite (SoC EDS) to secure the second-stage boot loader image.

Example

Arria 10

-
HPS DMA This HWLIB design example demonstrates how the DMA APIs are used to initialize the DMA, perform memory to memory transfers, and zero to memory transfers.

Example-AV
Example-CV
Example-A10

Readme-AV
Readme-CV
Readme-A10

Error correction code This HWLIB design example demonstrates the error correction code (ECC) APIs features for on-chip RAM, SD/MMC, quad serial peripheral interface (SPI), DMA and L2 cache. The example shows how to setup and enable ECC for each RAM, inject single/double bit errors and setup the interrupts for single/double bit error detections.

Example-AV
Example-CV
Example-A10

Readme-AV
Readme-CV
Readme-A10

GPIO This HWLIB design example demonstrates the usage of general-purpose input/output (GPIO) APIs to setup GPIO as output ports to drive HPS LEDs, and to setup GPIO as input ports for HPS push buttons. Example-AV
Example-CV
Example-A10
Readme-AV
Readme-CV
Readme-A10
I2C This HWLIB design example demonstrates the usage of I2C APIs to perform master read/write and slave read/write. This example demonstrates I2C communication with LCD screen, EEPROM memory as well as communication between two I2C modules. Example-AV
Example-CV
Example-A10
Readme-AV
Readme-CV
Readme-A10
Quad SPI This HWLIB design example demonstrates the usage of quad SPI APIs to perform reading and writing to the quad SPI with generic block I/O functions, perform data transactions using indirect mode and DMA mode. The example also demonstrates additional API features such as setting up MMU and caches. Example-AV
Example-CV
Readme-AV
Readme-CV
SD/MMC This HWLIB design example demonstrates the usage of SD/MMC APIs to initialize SD/MMC card, read and write using block I/O functions. Example-AV
Example-CV
Readme-AV
Readme-CV
Timer This HWLIB design example demonstrates how to use the Timer APIs for free-running timer, one-shot timer, watchdog timer, and global timer measurements. Example-AV
Example-CV
Example-A10
Readme-AV
Readme-CV
Readme-A10
Unhosted This HWLIB design example shows how to use UART for printf output instead of semihosting. It also demonstrates how to boot a bare-metal program from a SD card. Example-AV
Example-CV

Readme-AV
Readme-CV

SPI This HWLIB design example demonstrates the usage of the SPI APIs to communicate between two SPI modules connected through the FPGA fabric.

Example-AV
Example-CV
Example-A10

Readme-AV
Readme-CV
Readme-A10
HPS Peripheral Mapping to FPGA This design example shows how to route the hard processor system (HPS) EMAC and I2C peripherals into the FPGA fabric and connect them to FPGA I/O. Example Readme
Power Optimization This HWLIB design example illustrates the use of WFI or WFE calls that put the calling processor core into clock gating mode to save power. Example Readme
Shared Memory Partition  This design examples illustrates how to configure and test the memory protection rules for the hard processor system (HPS) SDRAM Controller. Example Readme

 

相关链接

其他实例

 

英特尔设计实例主要供英特尔 FPGA 设备和工具的注册用户使用,而且这些用户需拥有 Quartus II 或 Quartus Prime 软件许可证。如欲购买 Quartus II 订阅版软件,请访问eStore 或者联系您当地的代理商。

 

设计实例免责申明

上述设计实例仅限用于英特尔公司的设备,英特尔公司保留其所有权。这些设计实例以“概不保证”的方式提供,以便于协调管理;英特尔明确表示不提供任何形式的(明示或暗示的)陈述或担保;包括但不限于对适销性、不侵权和特定用途适用性等的担保。英特尔明确表示不推荐、不建议以及不要求把这些设计实例和其他非英特尔公司提供任何产品搭配使用。