Altera is the leader in digital signal processing (DSP) performance for FPGAs. For DSP designs using FPGAs, higher performance translates directly to lower system costs by allowing more channels to be processed per FPGA.
A recent set of benchmarks compared the performance of Altera's and Xilinx's high-performance and low-cost FPGA device families using DSP intellectual property (IP) cores provided by each vendor. The benchmark results of DSP IP from each vendor show:
- For high-density FPGAs: Altera's Stratix® II FPGAs offer 1.5x higher DSP performance than Virtex-4 FPGAs
- For low-cost FPGAs, Altera's Cyclone® II FPGAs offer 2x higher DSP performance than Spartan-3 FPGAs
Stratix II FPGAs seamlessly integrate the embedded DSP blocks that operate at up to 450 MHz with high-performance adaptive logic module (ALM) logic structure and routing fabric to deliver the highest possible performance for your DSP designs. Based on the results, all benchmarked DSP IP core designs for Virtex-4 achieved a maximum frequency below 370 MHz, which is well under the claimed embedded multiplier performance.
The benchmark suite includes nine IP implementations in three distinct IP groups: Fast Fourier Transform (FFT), Finite Impulse Response (FIR) filter, and Forward Error Correction (FEC). Figure 1 shows the comparison of high-performance families, and Figure 2 shows the comparison of the low-cost families for each design.
Figure 1. DSP IP Performance Benchmark Data Comparing Stratix II and Virtex-4 FPGAs
Figure 2. DSP IP Performance Benchmark Data Comparing Cyclone II and Spartan-3 FPGAs
Note:
- The Spartan-3 family cannot support the required number of dedicated multipliers for this design.
Table 1 shows the benchmarking software setup and the device speed grade information.
| Table 1. Benchmark Setup and Device Speed Grade Information | ||||
| FPGA Category | FPGA Family | Speed Grade | Synthesis Tool | Place-and-Route Tool |
|---|---|---|---|---|
| High-Performance FPGAs | Altera® Stratix II | Fastest (-3) | QIS (1) | Quartus® II software version 5.0 |
| Xilinx Virtex-4 | Fastest (-12) | XST (1) | ISE 7.1i Service Pack 1 | |
| Low-Cost FPGAs | Altera Cyclone II | Fastest (-6) | QIS (1) | Quartus II software version 5.0 |
| Xilinx Spartan-3 | Fastest (-5) | XST (1) | ISE 7.1i Service Pack 1 | |
- QIS: Quartus Integrated Synthesis; XST: Xilinx Synthesis Technology
Table 2 provides the detailed parameterization information for DSP IP cores used in these performance benchmarks. The suite includes common configurations used in typical DSP designs. All cores were generated using Altera MegaWizard® Plug-In Manager and Xilinx CoreGenerator. (See more information on performance benchmarking methodology)
| Table 2. DSP IP Core Performance Benchmark Core Information | ||||
| Core Group | Core Version | Core Name | Core Description | |
|---|---|---|---|---|
| Altera | Xilinx | |||
| 1,024-point FFT | 2.1.2 | 3.1 | FFT1 | Burst Architecture, 16-bit Data & Twiddle |
| FFT2 | Streaming Architecture, 16-bit Data & Twiddle | |||
| 128-tap, 1-channel, Embedded Multiplier-based FIR Filters | 3.2.1 | 5.1 | FIR1 | 64 clock/output, 16-bit data & coefficient |
| FIR2 | 64 clock/output, 8-bit data & coefficient | |||
| FIR3 | 16 clock/output, 8-bit data & coefficient | |||
| FIR4 | 4 clock/output, 8-bit data & coefficient | |||
| FIR5 | 1 clock/output, 8-bit data & coefficient | |||
| FEC | 3.6.0 | 5.1 | Reed Solomon | Digital Video Broadcast Standard, continuous decoding, half key size, 8-bit/symbol |
| 4.2.0 | 5.0 | Viterbi | Parallel architecture, 3-bit soft width, 7 constraint length, 66 trace back length | |
