DSP Applications Using Stratix II Devices
Stratix® II devices offer several digital signal processing (DSP) features that provide exceptional data-processing capability for DSP applications, featuring DSP blocks, TriMatrix™ memory, and ternary adder support in adaptive logic modules (ALMs). Stratix II devices offer a more flexible and cost-effective solution than discrete digital signal processors do. Stratix II devices are ideal for image processing, military, wireless, broadcast, and medical applications.
These simple case studies highlight the benefits of Stratix II devices for DSP applications:
Video and Image Processing
Altera's Video and Image Processing Suite provides a set of common intellectual property (IP) cores used in many applications requiring graphics processing. A number of these cores, especially the 2D and 2D median filters, take advantage of the embedded DSP blocks in the Stratix II architecture (see also FIR Filter below). The serial digital video interface (SDI) standard can be implemented using the Stratix II GX family of FPGAs with embedded transceivers. High-performance on-chip memories and high-speed external memory interfaces allow the buffering and storage of image data at speeds that support high definition (HD) video and image processing.
By combining several of the cores, a complete video processing system can be created that combines several video sources with an on-screen display into one video output. This type of processing is widely used in medical imaging, multi-channel and military surveillance, and HD videoconferencing.
Digital Down Converter
A digital down converter (DDC) is commonly used in third-generation (3G) wireless systems for translating signals from a broadband frequency to the baseband frequency. A typical DDC implementation consists of a numerically controlled oscillator (NCO), a mixer, a cascaded integrator comb (CIC) filter, and a pulse-shaping decimator filter (shown in Figure 1).
A single-channel DDC can be designed using an NCO, two 18-bit multipliers, a decimate-by-eight CIC, a decimate-by-two 21-tap finite impulse response (FIR) filter, and a decimate-by-two 63-tap FIR filter.
Figure 1. Generic DDC Block Diagram
Note to Figure 1:
- PLD = Programmable logic device
FIR Filter
FIR filters are one of the most commonly used structures for implementing DSP algorithms. FIR filters are based on the sum of product terms where each product term is calculated by multiplying a coefficient and a delayed data input. Altera’s Stratix II embedded DSP blocks feature dedicated multipliers and adders that are optimized for calculating product term sum. Each Stratix II DSP block is capable of running up to 450 MHz. The dedicated multipliers reduce the FPGA logic resource needed and improve overall clock speeds.
For multipliers implemented in logic, the three-input adder structure supported in the Stratix II device family can significantly increase performance by reducing the number of add stages. The logic resource required for implementing a logic-based multiplier is also greatly reduced.
NCO
Altera's NCO Compiler generates high-precision sinusoidal waveforms for use in communication systems as intermediate frequency (IF) mixer oscillators and as reference generators in carrier recovery circuits such as all-digital phase-locked loops (PLLs).
The high-performance dedicated multipliers can be used to generate low-latency IF carriers at sample rates in excess of 200 million samples per second (MSPS). A new multiplier-based architecture utilizes the DSP blocks in Stratix II devices to implement very high-precision, high-performance NCOs. The enhanced arithmetic mode of the Stratix II logic structure favors this algorithm; this leads to appreciable savings in logic resource usage over previous device families and yields tremendous performance enhancements for very high precision oscillators.
In this way, the architectural features of the Stratix II family allow you to obtain a high-performance NCO that can produce high-precision output waveforms and still provide resource savings at the same time.
OFDM
OFDM is a technique to divide the spectrum equally. The sub-carrier in each frequency segment carries a portion of information. OFDM is similar to the frequency division multiplexing (FDM), except that each frequency is independent (orthogonal) of each other. A guard band is required between the frequencies to prevent interference in FDM; however, because the frequencies are orthogonal, OFDM allows spectrum overlapping and so increases the efficiency of the frequency band usage. Figure 2 shows a generic OFDM block diagram.
Figure 2. Generic OFDM Block Diagram
Notes to Figure 2:
- FEC = Forward Error Correction
- IFFT = Inverse Fast Fourier Transform
- RF = Radio Frequency
- FFT = Fast Fourier Transform
FFT
The butterfly unit is the basic computation unit of an FFT, which performs a complex multiplication of data points with sine and cosine values, which are referred to as twiddle factors. The Stratix II DSP block, which contains four 18-bit multipliers and adder blocks, is ideally suited to perform the complex multiplication operation in a single clock cycle.
Multipliers are the main contributor in determining the size and the performance of an FFT. Stratix II DSP blocks can easily meet the performance requirement without using FPGA logic resources. Furthermore, even when multipliers are implemented in Stratix II device logic, the three-input adder structure also greatly reduces the logic resource usage and boosts the performance compared to traditional four-input look-up table (LUT) architecture.
Correlator
Correlators are used in the channel cards in a 3G wireless basestation to recover or de-spread the data that is transmitted though spread-spectrum signals. Figure 3 shows the generic correlator block diagram.
Figure 3. Generic Correlator Block Diagram
The large adder tree takes up the bulk of the logic in a correlator design and is typically what limits the performance. The Stratix II architecture provides the three-input adder support that allows the addition of three numbers in an ALM. This adder structure reduces the add stages and boost the correlator’s performance. Furthermore, the logic resources needed for implementing this function are significantly reduced.
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