Altera provides a complete IEEE 802.3 10-Gbps Ethernet standard-compliant media access controller (MAC), 10GBASE-R physical coding sublayer (PCS), and physical media attachment (PMA) sublayer with XFI or SFI interface solution for a variety of chip-to-optical module, chip-to-chip, and backplane applications. The XFI is the electrical interface of XFP and SFI is the SFP+ enhanced 10-Gbps pluggable module high-speed serial electrical interface. Our XFI-SFI solution includes Altera® devices with integrated serial transceivers up to 12.5 Gbps, development kits, intellectual property (IP), collateral, and test data.
Stratix® IV GT and Stratix V GX, GS, and GT FPGAs provide fully integrated and silicon-proven XFI-SFI solutions for high-performance single or multiport 10-Gbps Ethernet (10GbE) applications and for connection to popular small XFP and small low-cost SFP+ optical modules. The solutions are designed to XFI and SFI specifications and have been tested in hardware. They utilize built-in transceivers to implement the XFI and SFI interface specifications in a single device, saving the system cost, board space, and power of external XFI or SFI serializer/deserializer (SERDES) devices. Table 1 provides an overview of the complete XFI and SFI solution.
| Table 1. Complete 10GbE with XFI and SFI Interface Solution | |
| Solution | Description |
|---|---|
| Transceiver | Integrated XFI and SFI transceivers arranged in blocks |
| Supported data rates | 10.3125 Gbps |
| Altera IP | |
| Development kits | |
| Stratix IV GT XFI-SFI characterization report | Contact your local Altera sales representative |
Technology Background
Altera's Stratix V GX, GS, and GT FPGAs have built-in serial transceivers with integrated hard IP blocks that provide a dedicated mode for implementing the complete 10GBASE-R PHY and XFI or SFI interface. Our Stratix IV GT FPGA implements 10GBASE-R PCS with soft IP in the FPGA fabric and 10GBASE-R PMA with XFI or SFI interface with integrated hard IP. Therefore, these devices allow the integration of many 10GbE MACs and 10GBASE-R PHYs with XFI-SFI interface into a single device.
Figure 1 shows the 10GbE MAC with integrated 10GBASE-R PHY as a complete 10GbE solution interfacing to various external 10GbE PHY devices. The Altera 10GBASE-R PHY MegaCore® function consists of two major functions: 10GBASE-R PCS, with integrated hard IP or soft IP, and 10GBASE-R PMA, with integrated hard IP and management logic soft IP (not shown). The 10GBASE-R PCS consists of a standard 64b/66b encoder and decoder, x58 scrambler and descrambler, gearboxes, receiver rate-matching and clock compensation FIFO buffer, and receiver word-alignment functions. The Altera 10GBASE-R PHY MegaCore function MegaWizardTM configuration tool can instantiate from 1 to 32 10GBASE-R interfaces in one instance for ease of use and sharing of management logic among multiple ports.
Figure 1. 10GbE MAC with 10GBASE-R PHY and Serial 10-Gbps XFI or SFI Interface Block Diagram
Notes:
- Some system channels may need EDC chip here
- 10GBASE-R PCS is in soft IP in Stratix IV GT and HardCopy® IV GT devices, but in hard IP in Stratix V GX, GS, and GT devices
- SFP = small form-factor pluggable module
MDIO = optional management data interface
XFP = 10 Gigabit Small Form Factor Pluggable module
XFI = 10-Gbps chip-to-chip electrical interface
SFP+ = 8.5 and 10-Gbps small form-factor pluggable module
SFI = SFP+ high-speed serial electrical interface
Figure 2 shows an example application of the 10GbE MAC with 10GBASE-R PHY in a multiport switch or router line card. In this design, the Altera FPGA aggregates 10GbE port traffic to an Interlaken controller in a highly integrated design. Then, the packet processor and traffic manager on the board process the packets and transfer them to a switch fabric card over a backplane.
Figure 2. Switch or Router Line Card with Multiple 10GbE MACs and XFI or SFI interface
Figure 3 shows an example application of the 10GbE MAC with 10GBASE-R PHY in multiple client ports of 10GbE to an OTN4 (100-Gbps) multiplexing transponder system. In this design, the Altera FPGA aggregates 10GbE port traffic to an OTN4 framer via a SFI-S interface (N x up to 11.3 Gbps). The data is then processed by forward error correction (FEC) and sent out by the 100-Gbps optical module to the OTN4 network.
Figure 3. OTN4 Muxponder Card with Multiple 10GbE MACs and XFI or SFI interface
The transceiver module in Stratix IV GT and Stratix V GX, GS, and GT devices with 10GBASE-R PHY and XFI-SFI interfaces are designed to the IEEE 802.3ae specifications and XFI and SFI specifications including functions, electrical interface specifications, jitter generation, jitter tolerance, clock frequency variations (+/- 100ppm), and delay constraints.
The 10GBASE-R PHY in a Stratix IV GT FPGA can operate with a 322.265625-MHz input reference clock. In the Stratix V GX, GS, and GT FPGAs, it can operate with a wider range of input reference clocks. This PHY provides a clock data recovery (CDR) receiver and a 10.3125-Gbps data serial transceiver with an AC-coupled differential interface and differential PCML drivers. The 10GBASE-R PHY internal parallel user logic interface is a single data rate XGMII (64 data + 8 control bits at 156.25 Mbps).
Ethernet is the most popular LAN technology expanding into metro and WAN networks, and it is the dominant wired networking protocol. It has evolved from a 1-MHz shared medium signal running on a coaxial cable to the present availability of numerous variants operating as fast as 100 Gbps. Altera's 10GbE solutions provide top-of-the-line performance for leading-edge network equipment development.
