- 10-Gbps Ethernet Reference Design
- MorethanIP 10-Gigabit Ethernet IP Cores
- XAUI Development Environments (PCI Express Development Board)
- Stratix IV (GX and E) FPGAs
- HardCopy IV (GX and E) ASICs
- Stratix II GX FPGAs
Altera provides a complete Media Access Controller (MAC) and PHY FPGA-based solution for a variety of chip-to-chip, backplane, and cable applications using the XAUI protocol as the basis. The solution includes FPGAs with integrated transceivers, development kits, intellectual property (IP) from MorethanIP, collateral, and test data. The solution enables simple, fast protocol implementation, which reduces design risk, shortens development times, and allows you to concentrate on the core functions of the system design.
Stratix® IV GX, HardCopy® IV GX, and Stratix II GX devices provide a fully integrated XAUI-compliant solution for high-performance applications, utilizing built-in transceivers to implement the protocol in a single device. Table 1 provides an overview of the complete XAUI solution.
| Table 1. Complete XAUI Solution | |
| Solution | Description |
|---|---|
| Transceiver | Integrated XAUI-compliant transceivers arranged in quads |
| Supported Data Rates | 3.125 Gbps, 3.75 Gbps |
| Partner IP Core | MorethanIP 10-Gigabit Ethernet IP cores |
| Development Boards | PCI Express Development Kit, Stratix II GX Edition |
| XAUI Characterization Report | Contact your local Altera® sales representative |
Technology Background
Altera’s Stratix IV GX, HardCopy IV GX, Stratix II GX, and Stratix GX devices are equipped with built-in transceivers that provide a dedicated mode for implementing the XAUI interface and allow the integration of multiple PHYs and MACs into a single FPGA. Embedded within the transceivers are dedicated rate-matching FIFO buffers, 8B/10B encoding and decoding functions, and word-alignment functions, all controlled by dedicated XAUI state machines. Each group of four channels also has built-in channel alignment circuitry to minimize skew across the interface. Figure 1 shows the 10-Gigabit Ethernet MAC with integrated PCS block diagram.
Figure 1. 10-Gigabit Ethernet MAC With Integrated PCS Block Diagram
Notes:
- SPI = serial peripheral interface
- SFP = small form-factor pluggable
- MDIO = optional management data interface
The Stratix IV GX, HardCopy IV GX, and Stratix II GX transceiver module meets all IEEE 802.3ae specifications, including jitter generation under 0.35 unit interval (UI) without pre-emphasis and jitter tolerance of more than 0.60 UI, peak-to-peak total. The transceiver module matches the 802.3 sinusoidal jitter-tolerance mask requirement. The 3.125-Gbps x4 channel unidirectional data transfer rate for 10-Gigabit Ethernet complies with the IEEE 802.3ae XAUI definitions for linking physical-layer devices with upper-layer devices. Each transceiver module has 180-mW per channel power dissipation, including receiver, transceiver, clock data recovery (CDR), bias circuit and phase-locked loop (PLL), and maximum pre-emphasis.
The XAUI transceiver module provides a 156-MHz input reference clock and parallel interface along with 4-channel CDR receiver and 4-channel transceiver arrays, an AC-coupled differential interface, and differential PCML drivers. The transceiver module also incorporates a 1:16 serializer/deserializer (SERDES) with a 16:20 gearbox, 8B/10B coding, and lane alignment. The transceivers offer up to 500 percent pre-emphasis and up to 17 dB equalization to compensate high-frequency losses.
Altera offers an array of silicon-proven 10-Gigabit MAC cores with built-in support for the XGMII, XAUI, XSBI (64B/66B PCS layer) interfaces, and OC-192. Built-in support is also provided for flow control, MII management, address-based filtering, and statistics counters for RMON and SNMP. The 10-Gigabit Ethernet MAC layer and reconciliation sub-layer core is compliant with the IEEE 802.3ae specification and supports multiple custom switch fabric enhancements to interface Altera's Stratix IV GX, HardCopy IV GX, and Stratix II GX devices directly to several 10-Gigabit Ethernet switch devices.
Altera is the first FPGA vendor delivering a multi-gigabit and 10-Gigabit Ethernet PCI Express host adapter card development kit. The host bus adapter, called the Stratix II GX PCI Express Development Kit, is built with Altera's Stratix II GX EP2SGX90 and EP2SGX130 devices, with up to 20 multi-gigabit transceivers accelerating the convergence of network and storage applications using 10-Gigabit Ethernet technology.
Ethernet is by far the most popular LAN technology and it is the dominant wired networking protocol. It has evolved from a 1-MHz shared medium signal running on coaxial cable to the present availability of numerous variants operating as fast as 10 Gbps. 10-Gigabit Ethernet provides top-of-the-line performance for leading-edge network development.
