The Common Electrical I/O (CEI) 6G implementation agreement specifies the transmitter, receiver, and interconnect channel associated with 6+ Gbps interfaces for application in high-speed backplanes, chip-to-chip interconnects, and optical modules. Also included are the jitter definition and measurement methodologies associated with CEI interfaces. THE CEI-6G specification has been adopted by emerging chip-to-chip protocols such as Interlaken.
CEI-6G is an electrical interface and does not define a protocol or intellectual property (IP) functionality. The implementation agreement specifically excludes any pin-out or connector information, management interface, or higher level data protocol. The implementation agreement is maintained by the Optical Internetworking Forum (OIF), which currently includes over 100 participating companies, including Altera.
Altera® devices that are compliant with the OIF CEI-6G implementation agreement include Stratix® V FPGAs (up to 66 channels), HardCopy® V ASICs (up to 48 channels), Stratix IV FPGAs (up to 48 channels), HardCopy IV ASICs (up to 36 channels), and Stratix II GX FPGAs (up to 20 channels). You can use these devices to implement any interface based on the CEI-6G agreement.
Related Links
Devices
Characterization
- Stratix II GX Characterization Results
- CEI-6G Characterization Report available upon request; contact your local Altera sales office
