The Common Public Radio Interface, (CPRI), is an initiative to define a publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors and preserves the software investment made by wireless service providers.
Conventional basestations are located adjacent to the antenna in a small hut at the base of the antenna tower. Finding suitable sites can be a challenge because of the footprint required for the hut, the need for structural reinforcement of rooftops, and the availability of both primary and backup power sources.
CPRI allows the use of a distributed architecture where basestations, containing the REC, are connected to remote radio heads via lossless fibre links that carry the CPRI data. This architecture reduces costs for service providers because only the remote radio heads containing the RE need to be situated in environmentally challenging locations. The basestations can be centrally located in less challenging locations where footprint, climate, and availability of power are more easily managed.
Figure 1 shows common CPRI network topologies. The blue lines represent the CPRI links; in most cases CPRI links are between an REC and RE modules or between 2 RE modules in a chain configuration.
Figure 1. CPRI Network Topologies
The CPRI specification addresses the details of the interface shown in Figure 2.
Figure 2. CPRI Interface
Meeting CPRI Latency Requirements
Altera's Stratix® IV FPGAs, Arria® II GX FPGAs, Cyclone® IV GX FPGAs, and HardCopy® IV GX ASICs include new transceiver enhancements that make it easy to meet the stringent deterministic latency requirements of the CPRI specification. As CPRI continues to evolve and line rates push upward, implementing the link layer in an FPGA is the easiest, most flexible, and cost effective solution.
Altera’s transceiver FPGAs and HardCopy ASICs, used in conjunction with a CPRI intellectual property (IP) core optimized for FPGAs, are ideal platforms for CPRI system implementation (see Table 1).
| Table 1. CPRI System Implementation | |||||
| CPRI Line Rate (Mbps) | Stratix IV GX FPGAs | Arria II GX FPGAs | HardCopy IV GX ASICs | Stratix II GX FPGAs | Cyclone IV GX FPGAs |
|---|---|---|---|---|---|
| 614.4 |
|
|
|
|
 |
| 1228.8 |
|
|
|
|
|
| 2457.6 |
|
|
|
|
|
| 3072.0 |
|
|
|
|
|
| >3072.0 |
|
- |
|
|
- |
