Interlaken
Interlaken is a scalable, chip-to-chip interconnect protocol designed to enable transmission speeds from 10 to 100 Gbps and beyond. Using the latest serializer/deserializer (SERDES) technology and a flexible protocol layer, Interlaken minimizes the pin and power overhead of chip-to-chip interconnect and provides a scalable solution that can be used throughout an entire system. The scalability comes from Interlaken’s ability to run over a variable number of lanes with no inherent limit on the data rate per lane.
Addressing the shortcomings of existing chip-to-chip protocols, Interlaken combines the channelization and flow control attributes of SPI4.2 with the long reach and low pin count requirements of XAUI. Bundles of serial links create logical chip to chip connections with multiple channels, backpressure capability, cyclic redundancy check (CRC)-based data integrity checking, and flexible lane configuration.
Altera’s high-speed Stratix® IV GX FPGAs (up to 32 channels at rates up to 8.5 Gbps, and up to 16 additional channels at rates up to 3.2 Gbps), HardCopy® IV GX ASICs (up to 16 channels at rates up to 6.5+ Gbps, and up to 8 additional channels at rates up to 3.2 Gbps) and Stratix II GX FPGAs (up to 20 channels at 6.375 Gbps), used in conjunction with an Interlaken intellectual property (IP) core optimized for FPGAs, provide an ideal platform on which to implement one or more Interlaken interfaces.
Sarance's Interlaken IP (IIPC) core is a highly efficient implementation of Interlaken. The IIPC core is available today for use with FPGAs. The FPGA implementation is specifically optimized to take advantage of the advanced structures available in modern FPGAs. The family consists of cores ranging from 10 to 40 Gbps, supporting any number of serializer/deserializer (SERDES) lanes. Each core is fully compliant to the Interlaken revision 1.1 specifications and provides a cost effective, risk free, and quick time-to-market solution.
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