OBSAI
The Open Base Station Architecture Initiative (OBSAI) was formed to create standards, reduce costs, and ultimately create an open market for cellular base transceiver stations.
A base transceiver station (BTS) has four main modules: RF, baseband, control, and transport. The RF module receives signals from portable devices and converts them to digital data. The baseband module processes the encoded signal and brings it back to baseband before transmitting it to the terrestrial network via the transport module. Coordination between these three functions is maintained by a control module.
OBSAI seeks to meet its objective for open market BTS components by defining standard interfaces for the four modules. In the OBSAI specification, interfaces between modules are known as reference points (RP). RP1 is the interface that allows communication between a control module and the other three modules. RP2 provides a link between the transport and baseband modules, and RP3 connects the baseband and RF modules. The focus of the industry today is achieving lower cost RF modules and power amplifiers, as these components account for about 50 percent of the typical BTS cost. Consequently, the RP3 definition is the most critical OBSAI specification. As OBSAI evolves, an FPGA implementation of the RP3 specification is proving to be the simplest and most flexible solution.
Altera offers a number of FPGAs and ASICs with embedded transceivers that offer a high degree of programmability along with predictable latency. The high-speed Stratix® IV GX FPGAs, HardCopy® IV GX ASICs, and Stratix II GX FPGAs, used in conjunction with an OBSAI intellectual property (IP) core, are ideal platforms for OBSAI system implementation (see Table 1). The transceiver implementation in these devices includes clock data recovery, serializer/deserializer (SERDES), pattern detector, word aligner, and 8B/10B encoder/decoder, all of which are required to implement the physical layer of the OBSAI RP3 specification.
| Table 1. OBSAI System Platforms |
| OBSAI Line Rate (Mbps) |
Stratix IV GX FPGAs |
HardCopy IV GX ASICs |
Stratix II GX FPGAs |
| 768 |
 |
|
|
| 1536 |
|
|
|
| 3072 |
|
|
|
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