Altera provides a complete system solution to help you successfully interface Altera® FPGAs and HardCopy® ASICs to a variety of SRAM devices. SRAM devices offer extremely fast access times—approximately four times faster than DRAM—but are much more expensive to produce. Unlike DRAM, SRAM does not need to be refreshed periodically to prevent data loss through leakage. SRAM devices are capable of storing data as long as the device is supplied with power; if the power is turned off, the contents are lost. Typical systems require both SRAM (for performance critical applications) and DRAM memory (for all other applications).
QDR and QDR II SRAM Devices
QDR memory devices allow two ports to run independently at DDR, which results in four data items per clock cycle. QDR SRAMs enable you to maximize bandwidth by allowing operation at data rates above 200 MHz. The QDR architecture allows you to reach these speeds without the possibility of bus contention.
The QDR consortium, which consists of Cypress Semiconductor, Integrated Device Technology (IDT), Micron Technology, and NEC Corporation, developed the QDR architecture. QDR is designed to meet the high-performance needs of high-speed networking applications.
ZBT SRAM Devices
Zero-bus turnaround (ZBT) SRAM is a synchronous burst SRAM with a simplified interface that provides higher bandwidth and efficient bus utilization by eliminating turnaround cycles and idle cycles between read and write operations. IDT, Micron, and Motorola jointly developed the ZBT SRAM architecture, which is optimized for networking and telecommunications applications.
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