This web page provides a summary of hardware test results for Stratix® FPGAs interfacing with Quad Data Rate II (QDRII) SRAM memory devices.
Highlights from the test results include:
- Hardware-proven system performance exceeds 800 Mbps (Read and write combined data rate, 200 MHz clock frequency) with Stratix FPGAs.
- Measurement waveforms correlate well with simulation waveforms.
Memory System Test Environment
Table 1 displays the test parameters for Stratix FPGAs interfacing with QDRII SRAM devices.
| Table 1. Experiment Setup for Stratix & QDRII SRAM System Test | |
| Test Parameter | Description |
|---|---|
| Test Board | QDRII SRAM Stratix Hardware Reference Platform |
| Stratix Device | EP1S40F1020-5 |
| Memory Device | Cypress CY7C1313V18-200BZC |
| Memory Interface I/O Type | HSTL1 |
Board Setup
The QDRII SRAM Stratix Hardware Reference Platform includes the following: one Stratix EP1S40F1020 device, two 18-MBit QDRII SRAM devices (located on bank 7 of the Stratix FPGA), configuration devices, standard communication ports, system monitoring, buttons, switches, LEDs, debug ports for logic analyzer connectors, and characterization components.
The followng photo is this QDRII SRAM Stratix Hardware Reference Platform.
Block Diagram
Altera thoroughly tested the Stratix QDRII SRAM memory interface solution on the hardware platform. Figure 1 shows a top-level block diagram of the system.
Figure 1. Block Diagram of QDRII SRAM Memory Controller on a Stratix Device
Test Results
Test results found the following:
-
QDRII SRAM Controller implemented on Stratix FPGA exceeds the performance of 800 Mbps (read and write combined data rate, 200 MHz). Shown in Figure 2.
- Actual hardware measurement results were compared with simulation results to confirm the correlation.
Figure 2. QDRII SRAM Single-Bit Write Data Eye-Diagram - 200 MHz
Conclusion
QDRII SRAMs greatly increase memory bandwidth in applications like routers and asynchronous transfer mode (ATM) switches. The hardware test results from interfacing Altera's Stratix devices with QDRII SRAM memory devices show how Altera FPGAs can reduce time-to-market and provide low-risk for new design implementation.
Contact your local Altera Field Applications Engineer (FAE) for a demonstration.
