Memory Solutions Center—ZBT SRAM
Zero-bus turnaround (ZBT) SRAM with no bus latency (NoBL) memory is a synchronous-burst SRAM with a simplified interface that fully uses available bandwidth. ZBT SRAM devices use the full bandwidth because they do not require turnaround cycles (that is idle cycles between read and write operations). In contrast, standard-synchronous burst SRAMs require turnaround cycles which significantly reduce the available bandwidth.
Altera® FPGAs support high-performance ZBT SRAM interfaces as shown in Table 1.
| Table 1. ZBT SRAM Memory Interface Performance Support in Altera FPGAs |
| Device |
Maximum ZBT SRAM Interface Performance |
| Stratix® |
200 Mbps (200 MHz) |
| Stratix GX |
200 Mbps (200 MHz) |
| APEX™ II |
200 Mbps (200 MHz) |
Technical Documentation
Altera offers technical collateral that contains information on device support for ZBT SRAM interfaces as shown in Table 2.
Software Support & Tools
Altera offers the tools that aid in the ZBT SRAM memory interface design process as shown in Table 3.
| Table 3. ZBT SRAM Software Support & Tools |
| Feature |
Applicable Device(s) |
| IBIS Models for I/O Buffers |
Stratix
Stratix GX
APEX II |
IP Cores & Reference Designs
Altera offers a reference design for ZBT SRAM controller intellectual property (IP) cores, as shown in Table 4, which can be used to interface with ZBT SRAM devices.
List of ZBT SRAM Vendors
Related Links
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