By Dr. Eric Bogatin
www.BeTheSignal.com
October 2007
“When someone says their power integrity flow cuts out the guess work, they are lying,” Scott McMorrow, President of Teraspeed, says. “It really doesn’t—it just cuts out part of the guess work.”
Unfortunately, there is still a lot of guess work that goes into the design of the power distribution networks (PDNs) in most FPGA and ASIC board designs. PDNs are complicated and there are tough questions to answer during the design process.
For example, what is the current spectrum for the core logic and the I/O drivers? Where are the parallel resonances of the capacitors’ series inductance and the circuit board planes? How much on-chip capacitance is there and how does it interact with the circuit board planes and package inductance? Is the PDN impedance low enough and are there any other parallel resonances in the circuit board?
Starting prices for software tools that address pieces of these questions begin in the $50k range and require considerable user skill. The consequences of designing the PDN incorrectly, or even just not getting it good enough, are voltage rail collapse on the core logic and ground or power bounce on signals, both of which result in glitches. If a very special bit pattern conspires to draw just the right amount of current at just the right frequency, it can be difficult to diagnose and correct.
The purpose of the PDN is to provide a low impedance path from the voltage regulating module to the pads of the chip and to provide low impedance for the return currents for all switching I/Os. Information alone is not enough for an engineer to implement a robust PDN. A Google search on power integrity design results in over three million hits. What’s an engineer to do?
A new component option for power delivery networks was recently introduced as a joint venture between Samtec and Teraspeed Consulting Group, the culmination of years of development.
“The PowerPoser interposer does what three million Google hits don’t do for you.” McMorrow says. “It enables worry-free FPGA power delivery design.”
The PowerPoser interposer takes the board region that would be devoted to the power and ground distribution, decoupling capacitors, and filters of a large chip and elevates it above the board, acting as an interposer directly beneath the BGA. Its footprint is 1:1 with the BGA, with signals passing through vertical vias and the power and ground connections seeing a high bandwidth, low impedance network.
The interposer, shown in Figure 1, is 25 to 30 mils thick, is composed of multiple, thin dielectric layers, with an array of low inductance X2Y capacitors, and provides a carefully tailored impedance profile that minimizes plane resonances and peak parallel resonances.
Figure 1. PowerPoser Interposer Cross Section (Photo Courtesy of Teraspeed)
McMorrow says the PowerPoser interposer incorporates a number of patent pending features, including high-performance materials, ultra-low inductance capacitor-to-device interconnects, and advanced resonance suppression techniques.
In a demonstration vehicle using a high pin count, high-performance FPGA, with the interposer under the device and no other decoupling components on the board, using the interposer reduced the ground and power bounce noise of the switching I/Os by a factor of eight over the same board implemented with the manufacturer’s recommended decoupling strategy. The jitter on clocked lines was reduced by a factor of three, because of less noise on the strobes and clock edges and cleaner triggering.
When I/O signals switch between power or ground reference lines, the asymmetric return currents create noise in the power or ground rails. This noise is injected into the board to affect the rest of the system. The wideband, low-impedance shunt of the PowerPoser across the power and ground rails filters this noise and minimizes the high-frequency currents injected into the board planes. This means less noise added to other signal lines and less contribution to EMI, generated directly or from external cables.
By removing the need for as many as 300 components in the board-level PDN of high performance FPGAs, routing channels around the BGA escape are freed up.
Best of all, it eliminates the guess work for the designer.
Each PowerPoser interposer must have a custom footprint for a specific device. Currently, Samtec has released one interposer design and plans on three additional designs by the end of the year. For more information, contact www.samtec.com/powerposer or www.teraspeed.com.
This and other signal integrity topics are covered in Eric’s public classes and online lectures, available from his website, www.BeTheSignal.com. Send your signal integrity technical questions to DoctorIsIn@BeTheSignal.com.
Bio: Eric is president of Bogatin Enterprises, whose mission is to set the standard for signal integrity training. He is the author of Signal Integrity - Simplified, published by Prentice Hall. Check out his public signal integrity classes posted on www.BeTheSignal.com. He can be reached at eric@BeTheSignal.com.
