Stratix IV FPGA Signal and Power Integrity

Stratix^® IV 40-nm FPGAs simplify the challenges of designing for signal integrity by providing transceivers with best-in-class jitter characteristics. Advanced features in those transceivers simplify PCB design and compensate for inevitable board losses through adaptive equalization, multi-tap pre-emphasis, programmable V_OD, and on-chip termination (see Table 1). Additional features are also included that enhance the Stratix IV FPGA die and package, resulting in excellent signal and power integrity and maximum user flexibility (see Table 2).

The Stratix II GX and the Stratix IV GX family of FPGAs are the only devices in the industry with the ability to automatically and continuously monitor and set the receive equalizer to the best eye opening (see Figure 1) for a particular high-speed interconnect and provide Plug & Play Signal Integrity, as seen on Stratix II GX FPGAs in this video.

Figure 1. 40-nm Eye Diagram at 8.5 Gbps per Second

Figure 1. Stratix IV FPGA Eye Diagram

Altera’s adaptive dispersion compensation engine (ADCE) technology, along with hot-socketing capability, allows you to load just one FPGA image for all card slots in your system, reducing inventory, characterization, and factory test costs. ADCE in production can continuously monitor and compensate for manufacturing variations as well as process voltage and temperature effects.

Feature	Specification	Benefits
*Table 1. Signal Integrity Features of Stratix IV GX Transceiver FPGAs*
Receiver Equalization	16-dB 4-stage filter	Delivers best-in-class signal integrity, enabling operation to 8.5 Gbps across lossy backplanes Can either be set manually or by using the ADCE adaptive equalizer, which monitors and continuously updates equalizer settings for the best eye opening
Programmable V_OD	400 mV to 1,400 mV	Enables you to select a level for system design or to meet a protocol standard
Pre-Emphasis	900% 3-taps	Dynamically programmable 3-tap transmitter pre-emphasis with up to 8,192 pre-emphasis levels to compensate for pre-cursor and post-cursor inter-symbol interference (ISI)
On-Chip Termination	0, 100, 150 differential	Simplifies board layout Removes need for additional PCB trace stubs

Pre-emphasis, equalization, and V_OD are all dynamically programmable in Stratix IV GX FPGAs. This allows you to change levels while the transceiver is operating, making it simpler to tune the interface for interoperability testing or to change a setting, depending on a board's location in a system. See Table 2.

Features	Benefits
*Table 2. I/O and Packaging Features for Optimal Signal Integrity*
8:1:1 User I/O, Ground, and Power Ratio	Provides low impedance return path for every I/O to reduce loop inductance and noise.
Optimized Die- and Package-Level Signal Return Path	Optimizes return path with low impedance to reduce loop inductance and noise.
Adjustable Slew Rate Control	Controls signal edge rate to reduce noise.
Staggered Output Delay Control	Spaces out simultaneous switching outputs (SSO) switching time to reduce simultaneous switching noise (SSN).
Dynamic On-Chip Termination	Dynamically controls on-chip termination for proper line termination and impedance matching, which helps prevent reflections on the transmission line. Eliminates the need for external termination resistors to lower system cost and simplify PCB design.
On-Package and On-Die Decoupling	Provides high-frequency decoupling and suppresses power noise. Reduces the number of external PCB decoupling capacitors to lower system cost and simplify PCB design.

Table 3 highlights the features and benefits of the high-speed differential signals of Stratix IV FPGAs.

Features	Benefit
*Table 3. High-Speed Differential Signaling*
LVDS Buffer Enhancement	Includes programmable pre-emphasis and programmable V_OD features to compensate for signal attenuation.
Dynamic Phase Alignment (DPA)	Compensates for skew in board layout, allowing source-synchronous I/O to operate at higher data rates, which increases the likelihood of successful PCB layout.
Soft-CDR	Soft-CDR circuitry at the receiver allows implementation of asynchronous serial interfaces with embedded clock at data rates up to 1.6 Gbps (for example SGMII, Gigabit Ethernet)

Stratix IV FPGA Signal and Power Integrity

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