Benchmarks comparing signal integrity results for Stratix® II and Virtex-4 FPGAs demonstrate a significant advantage for Stratix II.
| Figure 1: 1.0 Gigabits per Second LVDS IBIS Simulation Comparison of Stratix II and Virtex-4 Eye Diagrams |
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The benchmarks between Stratix II and Virtex-4 I/O signal integrity are based on simulations using IBIS I/O models from both Altera and Xilinx. In addition, simulations verifying the correlation of Altera’s Stratix II IBIS models versus lab measurements are shown to validate the Altera simulation results. The Virtex-4 IBIS models were downloaded directly from the Xilinx website and are assumed to be accurate. These comparisons and further technical information are available in the Signal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs white paper.
Pin Capacitance Measurements
The major difference between Stratix II and Virtex-4 signal integrity results is best explained by the relative difference in pin capacitance between the two FPGAs. The table below shows the pin capacitance values for different Stratix II and Virtex-4 I/Os. Stratix II I/O pin capacitance is less than half that of Virtex-4. Stratix II devices have the lowest pin capacitance in the FPGA industry. The pin capacitance numbers in this table were obtained from lab measurements.
| Table 1: Pin Capacitance Comparison Between Stratix II and Virtex-4 FPGAs | ||
| Pin Description | Stratix II | Virtex-4 |
|---|---|---|
| User I/O—Vertical (1) | 5.0pF | 12.5pF |
| User I/O—Horizontal (2) | 6.1pF | 12.5pF |
| Configuration Data Pins | 5.0pF | 11.0pF |
| Clock Pins—Top/Bottom CLK[4..7] and CLK[12..15] |
6.0pF | 11.0pF |
| Clock Pins—Left/Right CLK0, CLK2, CLK8, CLK10 |
6.1pF | 11.0pF |
| Clock Pins—Left/Right CLK1, CLK3, CLK9, CLK11 |
3.3Pf | 11.0Pf |
- Vertical I/Os. I/O standards supported are LVTTL, LVCMOS, PCI, PCI-X, HSTL-1.5V Class I and II, HSTL-1.8V Class I and II, SSTL-18 Class I and II, and SSTL-2 Class I and II.
- Horizontal I/Os. I/O standards supported are LVDS, HyperTransport™, LVTTL, LVCMOS, SSTL-2, and SSTL-18 Class I.
What If Stratix II Had High-Capacitance I/Os Like Virtex-4?
Altera ran simulations of a Stratix II device with its actual pin capacitance measurements compared to a Stratix II device with modified capacitance to match Virtex-4 I/O pin capacitance. These results demonstrate the impact of the 2X capacitance inherent in the Virtex-4 I/O pin structure.
| Figure 2: 1.0 Gigabit per Second LVDS IBIS Simulation Comparison of Stratix II With “Real” Pin Capacitance and Stratix II With 2X Pin Capacitance (as Virtex-4) |
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