文档资料 许可 在线购买 下载 全部页面 技术资料 产品型号

主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买

DSP   |   外部存储器   |   嵌入式处理   |   高速串行I/O   |   并行I/O   |   信号完整性   |   系统集成

器件       Arria GX       Stratix III       Stratix II    Stratix II GX           特性           特性结果       Cyclone III       Cyclone II       Stratix GX     基本原理       信号完整性基础       高速术语表     技术       即插即用信号完整性     信号完整性合作伙伴       设计服务     SI专家学习指导       介绍Bogatin博士       每月专栏

主页 > 技术中心 > 信号完整性 > Stratix II GX 打印此页 发送此页 Stratix II GX Signal Integrity Center This page contains links to Stratix® II GX FPGA design resources that help you develop, optimize, and verify your high-speed channel and board design and signal integrity. Plug & Play Signal Integrity with the industry’s first adaptive equalizer – Altera’s ADCE Transceiver dynamic reconfiguration to support multiple protocols, data rates and physical medium attachment (PMA) settings Reduce risk, development time, and cost with the new Stratix II GX high-speed board design advisor documents Evaluate the simultaneous switching noise in your design with the Stratix II GX early SSN estimator Learn how pre-emphasis and equalization link estimator (PELE) technology can take weeks off your Stratix II GX channel simulation Perform online characterization with the Stratix II GX eye diagram viewer Stratix II GX Device Handbook Stratix II GX Transceiver Architecture Overview (PDF) Selectable I/O Standards in Stratix II & Stratix II GX Devices (PDF) High-Speed Source-Synchronous Differential I/O Interfaces in Stratix II GX Devices (PDF) Package Information for Stratix II & Stratix II GX Devices (PDF) High-Speed Board Layout Guidelines (PDF)  Application notes Guidelines for Designing High-Speed FPGA PCBs (PDF) Stratix II GX SSN Design Guidelines (PDF) White papers Basic Principles of Signal Integrity (PDF) Conference papers Digitally Assisted Adaptive Equalizer in 90 nm With Wide Range Support From 2.5 Gbps-6.5 Gbps (PDF) (Presented at DesignCon 2007) Equalization Challenges for 6-Gbps Transceivers Addressed by PELE—A Software-Focused Solution (PDF) (Presented at DesignCon 2007) FPGA Design for Signal and Power Integrity (PDF) (Presented at DesignCon 2007) Pre-Emphasis and Equalization Parameter Optimization With Fast, Worst-Case/Multibillion-Bit Verification (PDF) (Presented at DesignCon 2007) Calibration Techniques for High-Bandwidth Source-Synchronous Interfaces (PDF) (Presented at DesignCon 2007) Device Models IBIS Models SPICE Models (Contact mySupport for more information) Transceiver ELDO Model Silicon Design-In Kit for Mentor Graphics® HyperLynx Platform Silicon Design-In Kit for Cadence Allegro Platform Simulation Tools and Technology PELE Technology Design-in kits for the Cadence Allegro platform and the Mentor Graphics ICX and HyperLynx tools contain validated models, topology files, layout constraints, example PCB files and footprints, tutorials, documentation, scripts, and other utilities. The design-in kits simplify and speed system modeling and PCB design. Transceiver Signal Integrity Development Kit, Stratix II GX Edition Targeted at evaluating transceiver signal integrity and features Shipped with easy to use configuration tools to simplify analysis 给本页评分   相关链接 Stratix II GX Eye Diagram Viewer Stratix II GX Signal Integrity Features Stratix II GX Protocols     注册索取最新邮件通知

请填写反馈意见   注册索取最新邮件通知

主页 | 产品 | 支持 | 最终市场 | 技术中心 | 教育与活动 | 公司介绍 | 在线购买  DSP | 外部存储器 | 嵌入式处理 | 高速串行I/O | 并行I/O | 信号完整性 | 系统集成  联系我们 | 站点帮助 | 网站导航 | 个人信息 | 法律申明  Copyright © 1995-2008 Altera International Limited, 香港九龙观塘观塘道388号创纪之城1期1座9楼11-18室 Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus和MegaCore是Altera公司的商标。