Part I
Part II
Introduction
Traditionally, digital design was a relatively uncomplicated affair. Designers could develop circuitry operating up to 30 MHz without having to worry about issues associated with transmission line effects because, at lower frequency, the signals remained within data characterization, allowing the system to perform normally. As system performance increased, however, the designer’s challenges became more difficult—the impact of higher frequency on the system meant the designer had to consider not only the digital properties, but also the analogue effects within the system.
Some of the biggest design challenges surround the I/O signaling where transmission line effects can have a significant effect on the data being sent. At low speeds, the frequency response has little influence on the signal, unless the transmission medium is particularly long. However, as speed increases, high-frequency effects take over, and even the shortest lines can suffer from problems such as ringing, crosstalk, reflections and ground bounce, seriously hampering the response of the signal—thus damaging signal integrity. In reality, these problems can be overcome by good design technique and by following simple layout guidelines. Altera provides the information to help overcome these issues.
Transmission Line Effects
Transmission lines are connections capable of carrying a signal between a transmitter and a receiver. Traditionally, transmission lines have been considered to be telecom-based cables operating over long distances. But as digital signals are transmitted over high speed, even the shortest passive printed circuit board (PCB) track will suffer from transmission line effects.
At low frequencies, a wire or a PCB track may be an ideal circuit without resistance, capacitance or inductance. But at high frequencies, alternating (AC) circuit characteristics dominate causing impedances, inductances and capacitances to become prevalent in the wire. A circuit model can be calculated, as shown in figure 1 below, and used to determine the characteristic impedance of the wire or track. This impedance of the wire is extremely important, as any mismatch within the transmission path will result in a reduction in quality of the signal.
Figure 1. Circuit Model Representation of a Transmission Line
Impedance Mismatch
Impedance mismatch is caused when the output impedance of the source (ZS), the impedance of the line (ZO) and the impedance of the receiver or load (ZL) are not equal. This will mean the transmitted signal is not fully absorbed within the receiver and the excess energy will be reflected back to the transmitter. This process will continue back and forth until all of the energy is absorbed. At high data rates, this has dangerous effects on the signal, causing overshoot, undershoot, ringing, and stair-step waveforms, all of which produce errors in signaling.
When the transceiver buffers are matched to the transmission media, the impedance mismatch problem is solved. In the case of a PCB, this can be achieved by careful selection of medium and by the use of the proper termination schemes.
Figure 2. Simple Parallel Termination
A number of different termination methods are used to overcome this problem, depending on the application. These can include simple parallel termination on Stratix® GX devices (as shown in figure 2), and can range to more complex resistor capacitor (RC) termination, in which an RC network provides a low-pass filter to remove low frequency effects, but passes the high-frequency signal.
Although external components can often help the situation, they require PCB real estate and may also require additional track stubs, which can introduce new problems.
Altera® high-speed I/O solutions provide on-chip programmable termination to reduce the need of external components. Both Stratix and Stratix GX devices provide on-chip termination technology. This technology provides receiver- and transmitter-driver impedance matching for serial and differential I/O. The high-speed transceiver blocks on the Stratix GX devices additionally provide a programmable termination scheme within the high-speed transceiver circuitry to support most high-speed I/O standards. In addition to termination, good PCB design techniques can be used to overcome these issues.
